IEEE Trans. VLSI Syst.
 2019
DOI: 10.1109/tvlsi.2019.2906820
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Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows

Shrinidhi Udupi
1
,
Joakim Urdahl
2
,
Dominik Stoffel
3
et al.
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Cited by 3 publications
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UVM-based Reusable Hardware Accelerator Verification Platform

Mengyao,
Jinxue,
Xia
2023
2023 8th International Conference on Integrated Circuits and Microsystems (ICICM)
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UVM-based Reusable Hardware Accelerator Verification Platform

Mengyao,
Jinxue,
Xia
2023
2023 8th International Conference on Integrated Circuits and Microsystems (ICICM)
1
0
0
0
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Properties First—Correct-By-Construction RTL Design in System-Level Design Flows

Ludwig
1
,
Urdahl
2
,
Stoffel
3
et al. 2020
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
7
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Cloud-Fog Automation: Vision, Enabling Technologies, and Future Research Directions

Jin
1
,
Yu
2
,
Kua
3
et al. 2024
IEEE Trans. Ind. Inf.
16
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