2022
DOI: 10.1109/tc.2020.3043476
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Exploiting Symmetrization and D-Reducibility for Approximate Logic Synthesis

Abstract: Approximate synthesis is a recent trend in logic synthesis where one changes some outputs of a logic specification, within the error tolerance of a given application, to reduce the complexity of the final implementation. We attack the problem by exploiting the allowed flexibility in order to maximize the regularity of the specified Boolean functions. Specifically, we consider two types of regularity: symmetry and D-reducibility, and contribute two algorithms to find, respectively, a symmetric and a D-reducible… Show more

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Cited by 7 publications
(8 citation statements)
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“…The minimum function (15) contains 11 inverted variables. This is one inverted variable more than in (14).…”
Section: The Results Of Boolean Function Minimization By the Visual-mmentioning
confidence: 99%
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“…The minimum function (15) contains 11 inverted variables. This is one inverted variable more than in (14).…”
Section: The Results Of Boolean Function Minimization By the Visual-mmentioning
confidence: 99%
“…Approximate synthesis is a recent trend of logical synthesis when some results of the logical specification change within the permissible error of the assigned application in order to reduce complexity and accelerate the implementation of the final digital component; it was considered in paper [14]. The task of synthesis is solved by using the permissible flexibility of technology to maximize the regularity of the assigned Boolean functions.…”
Section: Literature Review and Problem Statementmentioning
confidence: 99%
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