Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations

Denolf, Kristof; Bekooij, Marco; Cockx, J.; Verkest, D.; Corporaal, Henk

doi:10.1155/2007/84078

Cited by 21 publications

(17 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, we discuss another application: a multiple-reader, multiple-writer FIFO. Such FIFO in combination with distributed memory is useful in streaming applications [20,21]. Fig.…”

Section: B Distributed Shared Memory: Multi-reader/-writer Fifomentioning

confidence: 99%

Portable Memory Consistency for Software Managed Distributed Memory in Many-Core SoC

Rutgers

Bekooij

Smit

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

View full text Add to dashboard Cite

Abstract-Porting software to different platforms can require modifications of the application. One of the issues is that the targeted hardware supports another memory consistency model. As a consequence, the completion order of reads and writes in a multi-threaded application can change, which may result in improper synchronization. For example, a processor with out-of-order execution could break synchronization if proper fence instructions are missing. Such a bug can cause sporadic errors, which are hard to debug.This paper presents an approach that makes applications independent of the memory model of the hardware, hence they can be compiled to hardware with any memory architecture. The key is having a memory model that only guarantees the most fundamental orderings of reads and writes, and annotations to specify additional ordering constraints. As a result, tooling can transparently and properly implement fences, cache flushes, etc. when appropriate, without losing flexibility of the hardware design. In a case study, several SPLASH-2 applications are run on a 32-core software cache coherent MicroBlaze system in FPGA. Moreover, this approach also allows mapping to scratch-pad memories and a distributed shared memory architecture.

show abstract

“…Therefore, we discuss another application: a multiple-reader, multiple-writer FIFO. Such FIFO in combination with distributed memory is useful in streaming applications [20,21]. Fig.…”

Section: B Distributed Shared Memory: Multi-reader/-writer Fifomentioning

confidence: 99%

Portable Memory Consistency for Software Managed Distributed Memory in Many-Core SoC

Rutgers

Bekooij

Smit

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

View full text Add to dashboard Cite

show abstract

“…An approach to handle dynamic behavior (dynamic stream processing) has been proposed by Geilen and Basten in [32]. In [24], the authors present a new approach to express and analyze implementation specific aspects in CSDF graphs -a primary focus of this work -for computer vision applications with concentration only on the channel/edge implementation.…”

Section: Modeling and Transformationsmentioning

confidence: 99%

“…However, since many computer vision applications show behavior that can be successfully captured by CSDF graphs [24], it is imperative to look into efficient scheduling techniques for them.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design Methodology for Embedded Computer Vision Systems

Bhattacharyya

Saha

2009

Embedded Computer Vision

View full text Add to dashboard Cite

Computer vision has emerged as one of the most popular domains of embedded applications. Though various new powerful embedded platforms to support such applications have emerged in recent years, there is a distinct lack of efficient domain-specific synthesis techniques for optimized implementation of such systems. In this thesis, four different aspects that contribute to efficient design and synthesis of such systems are explored:(1) Graph Transformations: Dataflow modeling is widely used in digital signal processing (DSP) systems. However, support for dynamic behavior in such systems exists mainly at the modeling level and there is a lack of optimized synthesis techniques for these models. New transformation techniques for efficient system-on-chip (SoC) design methods are proposed and implemented for cyclo-static dataflow and its parameterized version (parameterized cyclo-static dataflow) -two powerful models that allow dynamic reconfigurability and phased behavior in DSP systems.

show abstract

“…Therefore, we discuss another application: a multiplereader, multiple-writer FIFO. Such a FIFO, in combination with distributed memory, is useful in streaming applications [15,40].…”

Section: Distributed Shared Memory: Multi-reader/-writer Fifomentioning

confidence: 99%

Programming models for many-core architectures: a co-design approach

Rutgers¹

View full text Add to dashboard Cite

It is unlikely that general-purpose single-core performance will improve much in the coming years. The clock speed is limited by physical constraints, and recent architectural improvements are not as beneficial for performance as those were several years ago. However, the transistor count and density per chip still increase, as feature sizes reduce, and material and processing techniques improve. Given a limited single-core performance, but plenty of transistors, the logical next step is towards many-core.A many-core processor contains at least tens of cores and usually distributed memory, which are connected (but physically separated) by an interconnect that has a communication latency of multiple clock cycles. In contrast to a multicore system, which only has a few tightly coupled cores sharing a single bus and memory, several complex problems arise. Notably, many cores require many parallel tasks to fully utilize the cores, and communication happens in a distributed and decentralized way. Therefore, programming such a processor requires the application to exhibit concurrency. Moreover, a concurrent application has to deal with memory state changes with an observable (non-deterministic) intermediate state, whereas singlecore applications observe all state changes to happen atomically. The complexity introduced by these problems makes programming a many-core system with a single-core-based programming approach notoriously hard.The central concept of this thesis is that abstractions, which are related to (manycore) programming, are structured in a single platform model. A platform is a layered view of the hardware, a memory model, a concurrency model, a model of computation, and compile-time and run-time tooling. Then, a programming model is a specific view on this platform, which is used by a programmer.In this view, some details can be hidden from the programmer's perspective, some details cannot. For example, an operating system presents an infinite number of parallel virtual execution units to the application-details regarding scheduling and context switching of processes on one core are hidden from the programmer. On the other hand, a programmer usually has to take full control over separation, distribution, and balancing of workload among different worker threads. To what extent a programmer can rely on automated control over low-level platform-specific details is part of the programming model. This thesis presents modifications to different abstraction layers of a many-core architecture, in order to make the system as a whole more efficient, and to reduce the complexity that is exposed to the programmer via the programming model. viFor evaluation of many-core hardware and corresponding (concurrent) programming techniques, a 32-core MicroBlaze system, named Starburst, is designed and implemented on FPGA. On the hardware architecture level, a network-on-chip is presented that is tailored towards a typical many-core application communication pattern. All cores can access a shared memory, but as this ...

show abstract

Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations

Cited by 21 publications

References 19 publications

Portable Memory Consistency for Software Managed Distributed Memory in Many-Core SoC

Portable Memory Consistency for Software Managed Distributed Memory in Many-Core SoC

Design Methodology for Embedded Computer Vision Systems

Programming models for many-core architectures: a co-design approach

Contact Info

Product

Resources

About