Exploiting the Logic-In-Memory paradigm for speeding-up data-intensive algorithms

Cofano, Mario; Vacca, Marco; Santoro, Giulia; Causapruno, Giovanni; Turvani, Giovanna; Graziano, Mariagrazia

doi:10.1016/j.vlsi.2019.02.007

Cited by 5 publications

(2 citation statements)

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“…Internal writings are executed to locally save the result of the operation. There are a few works belonging to this category, such as [21,22,23,24].…”

Section: State Of the Artmentioning

confidence: 99%

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

2019

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Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.

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“…Internal writings are executed to locally save the result of the operation. There are a few works belonging to this category, such as [21,22,23,24].…”

Section: State Of the Artmentioning

confidence: 99%

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

2019

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“…Furthermore, two or more cells can be combined to perform more complex operations. Another study in [19] proposes a systolic three-layer memory structure consists of memory, routing, and logic planes.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

et al. 2019

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Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 mm 2 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency ( FFT / s / area ) among the existing FFT processors in the current literature.

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