Exploring Disturb Characteristics in 2D and 3D Ferroelectric NAND Memory Arrays for Next-Generation Memory Technology

Abstract

Ferroelectric transistors are considered promising for nextgeneration 3D NAND technology due to their lower power consumption and faster operation compared to conventional charge-trap flash memories. However, ensuring their suitability for such applications requires a thorough investigation of array-scale reliability. This study specifically examines the suitability of hafniabased ferroelectric transistors for advanced 3D NAND applications, with a specific focus on establishing a disturb-free voltage scheme to ensure the reliability of ferroelectric transistors within the array. Our key finding highlights the crucial role of optimal pass voltage in achieving disturb-free operation in both 2D and 3D ferroelectric NAND arrays. Additionally, the study indicates that read disturb remains negligible when an appropriate read voltage is applied. These insights provide a practical strategy for achieving reliable operation in 2D and 3D ferroelectric NAND, highlighting the potential of hafnia-based ferroelectric materials to meet the evolving requirements of high-density and reliable NAND flash memory applications.