Exploring Fine-Grained Heterogeneity with Composite Cores

Lukefahr, Andrew; Padmanabha, Shruti; Das, Reetuparna; Sleiman, Faissal M.; Dreslinski, Ronald G.; Wenisch, Thomas F.; Mahlke, Scott

doi:10.1109/tc.2015.2419669

Cited by 8 publications

(9 citation statements)

References 33 publications

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“…One limitation from this approach is that the core operation is mutually exclusive. However, this is deliberate for our limit study as we are interested in single thread behaviour and it resembles the operation of the rst commercial HMP systems [6] and merged cores that share the front end [20,22,24]. e infrastructure can easily be extended to accommodate beyond for more than one pair of coupled cores, however the decision tree of migration combinations is signi cantly more complex and is beyond the scope of this paper.…”

Section: Methodsmentioning

confidence: 99%

“…Prior work on the existence of phases at ne granularity and their potential micromanagement has shown that it is possible to exploit their bene ts through a heterogeneous system with di erent back-ends sharing the same front end [12,[20][21][22]. Despite the claim, no experimental data is provided that reveals the actual existence of application phases that appear at a ne granularity nor are the circumstances under which they can be exploited explained.…”

Section: Related Workmentioning

confidence: 99%

“…To reduce overall system slowdown when migrating, several studies propose the implementation of dedicated hardware to e ciently handle the transfer without any so ware intervention [12,13,18,21,26] and also fusing cores to share the front-end [20,22,24]. However, as hybrid designs are too complex to implement, it is worth investigating a simpler approach determining which components contribute most to the bene ts and sharing only those.…”

Section: Introductionmentioning

confidence: 99%

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Nucleus

Vougioukas

Sandberg

Diestelhorst

et al. 2017

ACM Trans. Embed. Comput. Syst.

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Heterogeneous multi-processors are designed to bridge the gap between performance and energy e ciency in modern embedded systems. is is achieved by pairing Out-of-Order (OoO) cores, yielding performance through aggressive speculation and latency masking, with In-Order (InO) cores, that preserve energy through simpler design. By leveraging migrations between them, workloads can therefore select the best se ing for any given energy/delay envelope. However, migrations introduce execution overheads that can hurt performance if they happen too frequently. Finding the optimal migration frequency is critical to maximize energy savings while maintaining acceptable performance. We develop a simulation methodology that can 1) isolate the hardware e ects of migrations from the so ware, 2) directly compare the performance of di erent core types, 3) quantify the performance degradation and 4) calculate the cost of migrations for each case. To showcase our methodology we run mibench, a microbenchmark suite, and show that migrations can happen as fast as every 100k instructions with li le performance loss. We also show that, contrary to numerous recent studies, hypothetical designs do not need to share all of their internal components to be able to migrate at that frequency. Instead, we propose a feasible system that shares level 2 caches and a translation lookaside bu er that matches performance and e ciency. Our results show that there are phases comprising up to 10% that a migration to the OoO core leads to performance bene ts without any additional energy cost when running on the InO core, and up to 6% of phases where a migration to the InO core can save energy without a ecting performance. When considering a policy that focuses on improving the energy-delay product, results show that on average 66% of the phases can be migrated to deliver equal or be er system operation without having to aggressively share the entire memory system or to revert to migration periods ner than 100k instructions. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro t or commercial advantage and that copies bear this notice and the full citation on the rst page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permi ed. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior speci c permission and/or a fee. Request permissions from permissions@acm.org. Instructions per cycle Fig. 1. An excerpt of execution of dijkstra running on two di erent core types. Sampling at a higher resolution reveals phases that can potentially be exploited to increase e iciency. INTRODUCTIONIn today's embedded devices, performance is always tied to power constraints and energy e ciency. is happens because, while process technology scaling is enabling larger transistor densities, power per area has shown to increase beyond a certain thr...

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Section: Methodsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Nucleus

Vougioukas

Sandberg

Diestelhorst

et al. 2017

ACM Trans. Embed. Comput. Syst.

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“…In addition, leading studies in the literature try to select an appropriate core in multicore systems based on the needs of running applications [6], [9], [10]. Another area of research is based on architectural techniques to achieve similar performance figures of out-of-order processors with the help of simpler datapath structures requiring less power and area [2], [11], [12], [13], [14], [15], [16].…”

Section: Related Workmentioning

confidence: 99%

ShapeShifter: a morphable microprocessor for low power

Tokatli¹,

Güney²,

Sari³

et al. 2021

Turk J Elec Eng & Comp Sci

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A composite core contains large and small heterogeneous microengines. The most important property of composite cores is their ability to select the most proper microengine for running applications for saving power without sacrificing too much performance. To achieve this, a composite core tries to predict the performance of the passive microengine by collecting various processor statistics from the active microengine at runtime. In the method proposed in the literature, the microengine, which is more ideal for running the rest of the application, is determined by a migrationdecision circuitry that is bound to collected statistics and complex functions, which are run in a sequential manner. In this study, we propose the ShapeShifter architecture that holds a single out-of-order core to switch its mode of instruction execution between out-of-order and in-order modes. With a simple mode-change decision circuitry, which is bound to only two processor statistics, can save more than 25% power, more than 21% on energy-delay product, and more than 16% on energy-delay-square product on the average, by only sacrificing less than 5% of performance.

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“…Purely dynamic approaches take into account runtime information. They can be implemented at the architecture level [13,17,25,30,33], or at the virtual Figure 10. Time (Top) and Energy (Bottom) comparison between Astro and GTS (G).…”

Section: Related Workmentioning

confidence: 99%

Compiler-assisted adaptive program scheduling in big.LITTLE systems

Novaes

Petrucci²,

Gamatié

et al. 2019

Proceedings of the 24th Symposium on Principles and Practice of Parallel Programming

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Energy-aware architectures provide applications with a mix of low (LITTLE) and high (big) frequency cores. Choosing the best hardware configuration for a program running on such an architecture is difficult, because program parts benefit differently from the same hardware configuration. State-ofthe-art techniques to solve this problem adapt the program's execution to dynamic characteristics of the runtime environment, such as energy consumption and throughput. We claim that these purely dynamic techniques can be improved if they are aware of the program's syntactic structure. To support this claim, we show how to use the compiler to partition source code into program phases: regions whose syntactic characteristics lead to similar runtime behavior. We use reinforcement learning to map pairs formed by a program phase and a hardware state to the configuration that best fit this setup. To demonstrate the effectiveness of our ideas, we have implemented the Astro system. Astro uses Q-learning to associate syntactic features of programs with hardware configurations. As a proof of concept, we provide evidence that Astro outperforms GTS, the ARM-based Linux scheduler tailored for heterogeneous architectures, on the parallel benchmarks from Rodinia and Parsec.

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Exploring Fine-Grained Heterogeneity with Composite Cores

Cited by 8 publications

References 33 publications

Nucleus

Nucleus

ShapeShifter: a morphable microprocessor for low power

Compiler-assisted adaptive program scheduling in big.LITTLE systems

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