Exploring supply voltage and temperature variation on XOR-XNOR cells with conventional/non-conventional techniques

Abstract

This paper delves into a comprehensive exploration of conventional and unconventional design approaches applied in XOR-XNOR cells. These cells play a crucial role in various arithmetic logic circuits with substantial computational capacity within VLSI designs operating at low voltage and power levels. The paper investigates the difficulties linked with both conventional and non-conventional design strategies. Furthermore, it performs a relative evaluation of different XOR/XNOR cells documented in current literature concerning circuit design parameters. The results of this investigation indicate that the adoption of carbon nanotube field-effect transistor (CNTFET) technology in lower technology nodes significantly decrease circuit delay, while floating gate metal-oxide semiconductor (FGMOS) technology displays superior interpretation in terms of circuit power efficiency. The discussion also covers the utilization of FinFET technology in the creation of XOR/XNOR cells. This paper conducts an assessment of the voltage and temperature resilience of these XOR/XNOR cells. The analysis has been undertaken utilizing the HSPICE tool at 22nm technology node. The XOR/XNOR cell based on FGMOS demonstrates the highest resilience to voltage and temperature fluctuations. The major challenges encountered in the adoption of nonconventional technologies involve the lack of appropriate simulation models and the intricate fabrication processes. These challenges notably hinder the progress and adoption of these pioneering methodologies.