Exploring the performance of partially reconfigurable point-to-point interconnects

Abdali, El Mehdi; Pelcat, Maxime; Berry, François; Diguet, Jean-Philippe; Palumbo, Francesca

doi:10.1109/recosoc.2017.8016160

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…This is the case of [40], which introduces the concept of tunable connections (TCONs), implemented in the routing resources of a theoretical device architecture. A different approach is the reconfigurable crossbar called ρ-P2P proposed in [41]. In this work, the authors proposed saving all the possible routing configurations of the crossbar as PBS, in such a way that routing can be modified by reconfiguring only the frames containing routing resources, reducing the configuration time.…”

Section: Fine Granularitymentioning

confidence: 99%

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

et al. 2020

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Dynamic partial reconfiguration technique can be used to modify regions of an FPGA as large as the whole reconfigurable fabric or as small as individual logic elements. However, FPGA manufacturers have focused their efforts on designing tools that support the design of monolithic reconfigurable accelerators spanning large regions of the device. Nevertheless, in some applications, it is enough to fine-tune the accelerators' behavior instead of changing them entirely. In these cases, rather than allocating new accelerators, it is possible to reconfigure individual logic elements of the circuit, such as look-up tables or flip-flops. There is also an intermediate approach that targets the reconfigurability of accelerators composed of several tightly interconnected modules, such as overlays. In those architectures, it is possible to reconfigure only the modules that differ between the existing accelerator versions, thus reducing the reconfigurable footprint granularity. This paper proposes a classification of the approaches above, categorizing them as coarse, fine, and medium grain, respectively. There are neither commercial nor academic tools supporting multi-grain reconfiguration to take advantage of each granularity strength on commercial FPGAs. Differently, this paper proposes a tool called IMPRESS, that provides design-time and run-time support for multi-grain reconfiguration in Xilinx 7 Series FPGAs. Specific criteria are provided to combine the different granularity levels, trading off the benefits in terms of flexibility and performance, with different design and run-time costs. Two use cases in the image processing and neural network domains have been implemented to show how IMPRESS can build multi-grain reconfigurable systems.

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Section: Fine Granularitymentioning

confidence: 99%

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

et al. 2020

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“…It used regular interconnection for the communications between building blocks. A reconfigurable point-to-point interconnect is proposed in the approach of Abdali et al (2017) to provide a lightweight reconfigurable interconnect system. However, the previous work in Harkin et al (2009) and Carrillo et al (2012) have highlighted the challenges of supporting the irregular communication patterns of SNNs due to its Manhattan style interconnections.…”

Section: Related Workmentioning

confidence: 99%

Low Cost Interconnected Architecture for the Hardware Spiking Neural Networks

et al. 2018

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A novel low cost interconnected architecture (LCIA) is proposed in this paper, which is an efficient solution for the neuron interconnections for the hardware spiking neural networks (SNNs). It is based on an all-to-all connection that takes each paired input and output nodes of multi-layer SNNs as the source and destination of connections. The aim is to maintain an efficient routing performance under low hardware overhead. A Networks-on-Chip (NoC) router is proposed as the fundamental component of the LCIA, where an effective scheduler is designed to address the traffic challenge due to irregular spikes. The router can find requests rapidly, make the arbitration decision promptly, and provide equal services to different network traffic requests. Experimental results show that the LCIA can manage the intercommunication of the multi-layer neural networks efficiently and have a low hardware overhead which can maintain the scalability of hardware SNNs.

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Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching

Duhamel,

Pillement

2024

IEEE Access

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Exploring the performance of partially reconfigurable point-to-point interconnects

Cited by 3 publications

References 10 publications

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

Low Cost Interconnected Architecture for the Hardware Spiking Neural Networks

Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching

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