Exploring the use of approximate TMR to mask transient faults in logic with low area overhead

Gomes, Iuri A. C.; Martins, Mayler G. A.; Reis, André I.; Kastensmidt, Fernanda Lima

doi:10.1016/j.microrel.2015.06.125

Cited by 42 publications

(33 citation statements)

References 7 publications

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“…The output of the approximate modules differs from the original module for some of the input vectors, which helps in complexity reduction. The working principle for ATMR is as follows [10]:…”

Section: Atmr Voter and Reliabilitymentioning

confidence: 99%

“…In Verilog, a Single Event Transient (SET) is emulated by forcing a change in the state of the node by means of the force/release command. This simulated SET pulse is only logical, and therefore the sizing the electrical and temporal masking is not evaluated [10]. Thus, to test the voter circuit, force/release is exhaustively used at each node.…”

Section: Simulation Setupmentioning

confidence: 99%

“…TMR is one of the most general and effective hardening techniques. However, TMR suffers from a 200% area overhead problem [10,11]. Previous works on fault tolerance techniques have proposed the use of selective hardening methods such as Partial TMR [12], Selective TMR [13] and Approximate TMR (ATMR) [11,14,15] to overcome this area overhead issue of TMR without significantly compromising the fault masking.…”

Section: Introductionmentioning

confidence: 99%

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A Fault Tolerant Voter for Approximate Triple Modular Redundancy

2019

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Approximate Triple Modular Redundancy has been proposed in the literature to overcome the area overhead issue of Triple Modular Redundancy (TMR). The outcome of TMR/Approximate TMR modules serves as the voter input to produce the final output of a system. Because the working principle of Approximate TMR conditionally allows one of the approximate modules to differ from the original circuit, it is critical for Approximate TMR that a voter not only be tolerant toward its internal faults but also toward faults that occur at the voter inputs. Herein, we present a novel compact voter for Approximate TMR using pass transistors and quadded transistor level redundancy to achieve a higher fault masking. The design also targets a better Quality of Circuit (QoC), a new metric which we have proposed for highlighting the ability of a circuit to fully mask all possible internal faults for an input vector. Comparing the fault masking features with those of existing works, the proposed voter delivered upto 45.1%, 62.5%, 26.6% improvement in Fault Masking Ratio (FMR), QoC, and reliability, respectively. With respect to the electrical characteristics, our proposed voter can achieve an improvement of up to 50% and 56% in terms of the transistor count and power delay product, respectively.

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Section: Atmr Voter and Reliabilitymentioning

confidence: 99%

Section: Simulation Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Fault Tolerant Voter for Approximate Triple Modular Redundancy

2019

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“…In theory, DMR and TMR provide 100% probability of error detection (P detection ) at the expense of 100% and 200% area overheads, respectively. For reducing the huge hardware overheads incurred by TMR, some recent works focus on approximating the TMR for trading-off circuit reliability with the cost of mitigation [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection

et al. 2018

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Recently, concurrent error detection enabled through invariant relationships between different wires in a circuit has been proposed. Because there are many such implications in a circuit, selection strategies have been developed to select the most valuable implications for inclusion in the checker hardware such that a sufficiently high probability of error detection ( P d e t e c t i o n ) is achieved. These algorithms, however, due to their heuristic nature cannot guarantee a lossless P d e t e c t i o n . In this paper, we develop a new input-aware implication selection algorithm with the help of ATPG which minimizes loss on P d e t e c t i o n . In our algorithm, the detectability of errors for each candidate implication is carefully evaluated using error prone vectors. The evaluation results are then utilized to select the most efficient candidates for achieving optimal P d e t e c t i o n . The experimental results on 15 representative combinatorial benchmark circuits from the MCNC benchmarks suite show that the implications selected from our algorithm achieve better P d e t e c t i o n in comparison to the state of the art. The proposed method also offers better performance, up to 41.10%, in terms of the proposed impact-level metric, which is the ratio of achieved P d e t e c t i o n to the implication count.

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“…Therefore, how to solve the transient failure of digital circuits with low energy consumption has become a great challenge for the relevant designers [2]. In order to make the product reliable and sustainable, it is necessary to use the automatic repair technology to deal with the transient faults of digital circuits [3].…”

Section: Introductionmentioning

confidence: 99%

Study on self repairing method for transient fault and low energy consumption of digital circuit

Hui-ling¹

2018

Proceedings of the 2018 3rd International Workshop on Materials Engineering and Computer Sciences (IWMECS 2018)

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at present, most of the digital circuit transient fault repair methods need to be completed by manual processing, the repair efficiency is low and the energy consumption is high. For this, put forward a new kind of digital circuit fault transient low energy self repair method, design a repair system, which is mainly composed of self reconfiguration control module and execution module, self-discipline of the core control module is embedded Nios processor, digital circuit in the presence of transient fault, the wavelet neural network algorithm the diagnosis of digital circuit transient fault judging circuit, whether the normal operation of. The reconfiguration execution module consists of a logical computing node LC and an internal interconnection network. The main function is to maintain the function of the digital circuit and carry out the information transmission between the other modules. The experimental results show that the proposed method can effectively diagnose the fault, the success rate and the average fitness of the fault repair are high, and the overall performance is strong.

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Exploring the use of approximate TMR to mask transient faults in logic with low area overhead

Cited by 42 publications

References 7 publications

A Fault Tolerant Voter for Approximate Triple Modular Redundancy

A Fault Tolerant Voter for Approximate Triple Modular Redundancy

Input-Aware Implication Selection Scheme Utilizing ATPG for Efficient Concurrent Error Detection

Study on self repairing method for transient fault and low energy consumption of digital circuit

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