Fabrication and stacking of through-silicon-via array chip formed by notchless Si etching and wet cleaning of first metal layer

Abstract

We combined a "via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer" with the solder bonding process using Ar fast atom beam (FAB), and realized the fabrication and three-dimensional (3D) stacking of a high-density TSV array chip. The size of the TSV array was 76 × 500. The diameter and length of the TSV were 6 and 21-22 μm, respectively. As the TSV array chip was very thin (approximately 26 μm) and had a strip-like shape, it was fragile and warped by approximately 90 μm. Hence, an electrostatic chuck was introduced and the TSV array chip was stacked by using a soft material (Cu-Ni-Sn based solder) as a bump and performing low-pressing-load low-temperature bonding with Ar FAB. As a result, the warpage of TSV array chip was suppressed and the TSV array chip was stacked without causing damage to the TSV and Si region. In addition, it was confirmed that the (i) leakage current between TSV-bump pairs is small, (ii) multilayer wiring + TSV + bump connection exhibit low resistance, and (iii) daisy chain is perfectly connected to up to 38 000 TSVs. These results are due to the effects of notchless Si etching, wet cleaning of the first metal layer, introduction of an electrostatic chuck, low-pressing-load low-temperature bonding with a soft material, and Ar FAB. This process will facilitate the development of face-up type 3D stacked sensor systems.