Failure Analysis of a Chip Damaged by Electro-Static Discharge

Abstract

A process of failure analysis of a COMS chip damaged by Electro-Static Discharge (ESD) is presented. The method of the thermal image was used to locate the failure spot. To find out the root of the failure, the circuit principle and the layout of the chip were analyzed, and it was found that the layout design was not unreasonable. An ESD test was carried out to confirm the analysis. This work has reference significance for the failure analysis and reliability improvement of the integrated circuit product.