Fast, Accurate On-Chip Data Memory Performance Estimation

Abstract

In order to derive the optimal on-chip memory architecture for a given application, the embedded system designer must spend considerable time evaluating potential memory designs. However, tight time-to-market constraints enforce short design cycle time. In this paper we present an effective method to fast and accurately estimate the on-chip data memory performance which employs SPM and cache hybrid architecture for memory design space exploration. The key point is to estimate the performance of data cache by modeling data cache activity. Our method can be applied to all kinds of cache architecture and can statically categorize data cache misses into cold, conflict, and capacity misses, which can provide useful insights for designers to determine data cache architecture. Our evaluation results show that the proposed method can fast and accurately estimate the on-chip memory performance, thus can speedup design process of the on-chip memory architecture of an embedded system.