Fast and Accurate Inductance Extraction for Power Module Layout Optimization Using Loop-Based Method

Le, Quang Trung; Razi, Imam Al; Peng, Yarui; Mantooth, H. Alan

doi:10.1109/ecce47101.2021.9595620

Cited by 3 publications

(1 citation statement)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, the above-mentioned methods tend to be computationally costly when multiple consecutive inductance extractions are to be performed, what limits their usability for layout optimization. For optimization where the computational time of the parasitic inductance extraction is a crucial factor, more commonly used methods are to utilize lumped element circuit methodologies, such as with analytical microstrip equations available in PowerSynth [1] with some accuracy loss, or crude mesh analysis present in FastHenry [2]. Recent developments brought FFT-accelerated partial element equivalent circuit (PEEC) [3] and volume integral equation (VIE) [4] methods, achieving a significant reduction in computation time while maintaining good accuracy.…”

Section: Introductionmentioning

confidence: 99%

Ultra-Fast Power Module Inductance Estimation using Convolutional Neural Networks

Kubulus,

Michal Beczkowski,

Munk-Nielsen

et al. 2023

2023 IEEE Energy Conversion Congress and Exposition (ECCE)

View full text Add to dashboard Cite

The widespread usage of wide bandgap (WBG) semiconductors forces extra emphasis on the early estimation of the layout parasitic elements. Be it a printed circuit board or a power module, layout optimization is necessary to minimize the negative effects of present inductances. Unfortunately, multiple invocations of inductance extraction software can be timeconsuming. In this work, state-of-the-art convolutional neural networks (CNN) are applied in order to lower the time consumption of inductance estimation without compromising the accuracy.

show abstract