Fast and accurate technique for comparator offset voltage simulation

Omran, Hesham

doi:10.1016/j.mejo.2019.05.004

Cited by 8 publications

(6 citation statements)

References 8 publications

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“…A typical method to simulate the speed of the comparator is the transient simulation of the comparator that assesses whether the comparator accurately turns over within the specified time to judge whether the speed of the comparator meets the requirements [27]. The transient simulation test bench of the proposed comparator is shown in Figure 13.…”

Section: Transient Simulation Of the Comparatormentioning

confidence: 99%

Design of Self-Calibration Comparator for 12-Bit SAR ADCs

Tang

Wang

et al. 2023

Electronics

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A novel self-calibration comparator for a 12-bit 2.5 MSPS successive approximation register analog-to-digital converter (SAR ADC) applied in a touch microcontroller unit (MCU) with small area, high precision, fast response speed, and low-voltage detection is proposed in this paper. A combination of input/output offset storage (IOS/OOS) and an offset trimming circuit was employed to reduce the offset of the cascade preamplifier and the operational transconductance amplifier (OTA), a novel offset trimming circuit with a 5-bit digital controller was designed to further reduce the residual offset voltage, and an improved self-calibration technology was also implemented to compensate the conversion error in SAR ADC system to a minimum. Simulation and measured results show that the input-referred offset calibrating range is ±9.15 mV at 0.61 mV/step, the low-voltage detection of SAR ADC is realized by compensating the conversion error to a minimum, and the effective number of bits (ENOB) and figure of merit (FoM) at 5 V supply and 2.5 M/s rate in the 12-bit SAR ADC with a 95 nm CMOS are 11.33 bits and 726.6 fJ/conversion-step, respectively. The proposed self-calibration comparator applied in the SAR ADC system can automatically eliminate the offset voltage caused by nonidealities and meet the requirements of the touch MCU.

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Section: Transient Simulation Of the Comparatormentioning

confidence: 99%

Design of Self-Calibration Comparator for 12-Bit SAR ADCs

Tang

Wang

et al. 2023

Electronics

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“…Karşılaştırıcı Çıkışı ( ) Elde edilen çıkış geriliminde, uygulanan analog giriş ve referans işaretine göre geçiş noktasında Lojik 0 seviyesinden Lojik 1 seviyesine geçtiği gerilim ve zaman değerlerine bakılarak yükselen kenardaki of-set gerilim değerine ve gecikme zamanına bakılır [3].…”

Section: Latchunclassified

“…Aynı şekilde düşen rampa işareti uygulayarak da Lojik 1 seviyesinden Lojik 0 seviyesine geçtiği gerilim ve zaman değerlerine bakılarak inen kenardaki of-set gerilim değerine ve gecikme zamanına bakılır [3].…”

Section: Latchunclassified

“…arşılaştırıcı devreleri analog giriş işareti ile referans işaretini karşılaştırarak, giriş işaretinin referans işaretinden büyük ya da küçük olmasına göre çıkışta sayısal olarak Lojik 1 ya da Lojik 0 üreten bir devredir [1,2]. Karşılaştırıcı olarak kullanılan devre yapıları birçok analog, sayısal ve karışık sinyal uygulama sistemlerinin önemli bloklarından birisidir [3].…”

Section: Gi̇ri̇ş [Introduction]unclassified

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The Investigation of Auto-Zero Comparator Performance of Common Gate Differential Amplifier Based CMOS Inverter Circuit

Aytar¹

2020

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“…Dado que a resistência vista pelos drenos dos transistores de entrada é aproximadamente infinita quando clk C vai para o nível alto, a expressão da tensão de offset do comparador projetado é reduzida a Com o fim de caracterizar a tensão de offset do comparador, simulações pós-layout de Monte-Carlo incluindo variações de processo e mismatch foram realizadas. A simulação e caracterização da tensão de offset foi realizada com ajuda da técnica proposta em [48]. A tensão de offset é obtida a partir dos parâmetros da distribuição Gaussiana mostrada na Figura 40.…”

Section: Dimensionamentounclassified

Projeto de um conversor analógico-digital para um receptor UWB aplicado na detecção de câncer de mama em tecnologia CMOS.

Gonzalez¹

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This work presents the design of an 11 bits, 20-MS/s, Analog-to-Digital Converter (ADC) for an ultra-wideband (UWB) receiver applied in breast cancer detection in 180 nm CMOS technology.The architecture taken from the literature is known as successive approximation register (SAR). This architecture was selected because it is more efficient in energy terms compared to other architectures in order to achieve the design target of this project: a 20-MS/s ADC with a SNDR higher than 62 dB. A differential architecture was chosen to achieve a better common-mode disturbance rejection. The prototype ADC comprises a sample and hold circuit, a capacitive digital-to-analog converter (DAC), a dynamic comparator, and the logic control circuit which implements the SAR algorithm. Merged capacitor switching procedure was implemented, therefore, the differential DAC capacitor network serves both to a top-plate sampling of the input signal and subtracts the reference in the conversion process. Furthermore, the 11 bit ADC takes advantage of using 10 bit DACs, saving power and area. An asynchronous operation was selected to eliminate the need for an external high-frequency clock. To improve the linearity, a delay cell inside the asynchronous clock generator is implemented, allowing a larger settling time for the capacitive DAC.The designed ADC occupies 0.1 mm 2 and post-layout simulation results show that it achieves an ENOB of 10.73 bit at a sampling rate of 20 MS/s and an input tone at Nyquist rate. The power consumption is 2.89 mW at 1.8 V supply, thus achieving the figure of merits of Schreier (FoM S ) and Walden (FoM W ), 162 dB and 84 fJ/conv.-step, respectively. At 20-MS/s, 1,8-V, the DNL is +0,32/-0,29 LSB and the INL is equal to +0,33/-0,26 LSB.Experimental measurements were carried out to determine the performance of the designed ADC. From these tests, non-linearity issues were detected on the output signal of the ADC. These problems in the experimental phase of the design were analyzed, and a hypothesis was proposed to explain them. Based on theoretical and simulation analysis, it was found which the non-linearity issues may have happened owing to the parasitic inductive effect of the wire bonded chip.

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Fast and accurate technique for comparator offset voltage simulation

Cited by 8 publications

References 8 publications

Design of Self-Calibration Comparator for 12-Bit SAR ADCs

Design of Self-Calibration Comparator for 12-Bit SAR ADCs

The Investigation of Auto-Zero Comparator Performance of Common Gate Differential Amplifier Based CMOS Inverter Circuit

Projeto de um conversor analógico-digital para um receptor UWB aplicado na detecção de câncer de mama em tecnologia CMOS.

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