Fast and area efficient adder for wide data in recent Xilinx FPGAs

Abstract

Abstract-Most modern FPGAs have very optimised carry logic for efficient implementations of ripple carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof two inputs are used during normal addition. In this paper we present an architecture that compresses the carry chain length to N/2 in recent Xilinx FPGA, by utilising the LUTs better. This carry compression was implemented by letting some cells calculate the carry chain in two bits per cell, while some others calculate the summary output bits. In total the proposed design uses no more hardware than the normal adder. The result shows that the proposed adder is faster than a normal adder for word length larger than 64 bits in Virtex-6 FPGAs.

Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography

“…As we can see, the DSP blocks and a few multiplexers are part of the shared resources, whereas the dedicated modules contain mainly adders and subtractors. The adders and subtractors are implemented by efficient usage of fast carry chains [KG16]. The reduction logic for multiplications modulo Solinas prime is implemented using the target prime structure and involves only two additions and three subtraction operations.…”

Efficient hardware/software co-design for post-quantum crypto algorithm SIKE on ARM and RISC-V based microcontrollers

“…The basic building block of the architecture is the 88 bit integer adder and subtractor circuit. The integer adder and subtractor blocks are built using the design of [10] which proposed a fast FPGA adder using the six input dual output LUTs and carry chains. For a 434 bit integer addition operation, we need to use the 88 bit adder block five times.…”