Fast Fuzzy C-Means Clustering Based on Low-Cost High-Performance VLSI Architecture in Reconfigurable Hardware

Yeh, Yao-Jung; Li, Hui-Ya; Yang, Cheng-Yen; Hwang, Wen-Jyi

doi:10.1109/cse.2010.22

Cited by 2 publications

(2 citation statements)

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“…In addition to GHA architectures, many FCM architectures [ 20 – 22 ] have been proposed for image processing. However, some of these architecture are difficult to be extended for spike sorting.…”

Section: Related Workmentioning

confidence: 99%

“…The high hardware utilization increases the difficulty of integrating FCM with GHA on a single chip. An effective alternative to [ 20 , 21 ] is based on [ 22 ], which produces membership coefficients sequentially to reduce the area costs. In addition, the common factors of different membership coefficients are pre-computed by a shared circuit to further lower the hardware resource utilization.…”

Section: Related Workmentioning

confidence: 99%

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Efficient Architecture for Spike Sorting in Reconfigurable Hardware

Hwang

Lee

Lin

et al. 2013

Sensors

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This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

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Section: Related Workmentioning

confidence: 99%