Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks

Ferreira, Ricardo; Cardoso, João M. P.; Damiany, Alex; Vendramini, Julio C. Goldner; Teixeira, Tiago

doi:10.1016/j.sysarc.2011.03.006

Cited by 14 publications

(7 citation statements)

References 46 publications

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“…However, it is not easy to map a computation-intensive Data Flow Graph (DFG) onto a Reconfigurable Cell Array (RCA), because there are many constraints. In previous studies, researchers have presented a wide range of mapping algorithms based on a variety of CGRAs [2][3][4][5][6][7][8][9][10][11][12][13][14] . Yoon et al [2] proposed the spatial mapping algorithm, known as Split-Push Kernel Mapping (SPKM), to map several applications onto resource sharing and pipelining architecture.…”

Section: Introductionmentioning

confidence: 99%

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Chen

Wang

et al. 2021

Tsinghua Sci. Technol.

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Row Parallel Coarse-Grained Reconfigurable Architecture (RPCGRA) has the advantages of maximum parallelism and programmable flexibility. Designing an efficient algorithm to map the diverse applications onto RPCGRA is difficult due to a number of RPCGRA hardware constraints. To solve this problem, the nodes of the data flow graph must be partitioned and scheduled onto the RPCGRA. In this paper, we present a Depth-First Greedy Mapping (DFGM) algorithm that simultaneously considers the communication costs and the use times of the Reconfigurable Cell Array (RCA). Compared with level breadth mapping, the performance of DFGM is better. The percentage of maximum improvement in the use times of RCA is 33% and the percentage of maximum improvement in non-original input and output times is 64.4% (Given Discrete Cosine Transfor 8 (DCT8), and the area of reconfigurable processing unit is 56). Compared with level-based depth mapping, DFGM also obtains the lowest averages of use times of RCA, non-original input and output times, and the reconfigurable time.

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Section: Introductionmentioning

confidence: 99%

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Chen

Wang

et al. 2021

Tsinghua Sci. Technol.

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“…2. Many MINs topologies that all are equivalent in terms of topological, follow this general structure, such as the omega network, the flip network, the indirect binary n-cube, and the baseline and the reverse baseline networks [15,19,32,33]. In this general structure, switching stages are connected to each other by an interconnection pattern of links, which is known as a permutation network or a shuffle.…”

Section: General Structure Of Minsmentioning

confidence: 99%

“…According to the RBD of N×N ASEN in Fig. 30, its terminal reliability is given by the equation (15). (15) According to the ASEN-RL structure (shown in Fig.…”

Section: (4) (5)mentioning

confidence: 99%

“…30, its terminal reliability is given by the equation (15). (15) According to the ASEN-RL structure (shown in Fig. 14), its terminal reliability RBD for network size N×N is depicted in Fig.…”

Section: (4) (5)mentioning

confidence: 99%

“…According to equations (13), (14), (15), and (17), the results of terminal reliability analysis of ASEN and ASEN-RL for three different switch reliability, low switch reliability (r=0.9), middle switch reliability (r=0.95), and high switch reliability (r=0.99) and as a function of network size are shown in Fig. 33.…”

Section: (4) (5)mentioning

confidence: 99%

See 2 more Smart Citations

Rearranging links: a cost-effective approach to improve the reliability of multistage interconnection networks

Bistouni

Jahanshahi

2018

IJITST

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The use of multiprocessor systems is the main method for providing a high computational power. Multistage interconnection networks (MINs) are widely used to connect processors and memory modules in multiprocessor systems. Therefore, the design of an efficient MIN is an essential requirement for the development of multiprocessor systems. In addition, a critical parameter for any efficient interconnection network is reliability. However, the problem in the way of designing high-reliable interconnection networks is high hardware cost. To solve this problem, contribution of this paper is to propose a new approach to improve the reliability of the MINs, called the rearranging links. The proposed approach is implemented on two common MINs namely extra-stage shuffleexchange network (SEN+) and augmented shuffle-exchange network (ASEN). Meticulous analysis of terminal reliability proves that the proposed approach is an efficient method to improve the reliability of MINs. In addition, performed cost analysis confirms that utilizing it leads to emerge cost-effective MINs.

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Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture

Moura

Jordan

Beck

et al. 2018

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks

Cited by 14 publications

References 46 publications

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Rearranging links: a cost-effective approach to improve the reliability of multistage interconnection networks

Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture

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