FastTrackNoC: A NoC with FastTrack Router Datapaths

Ejaz, Ahsen; Sourdis, Ioannis

doi:10.1109/hpca53966.2022.00075

Cited by 3 publications

(5 citation statements)

References 32 publications

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“…There are studies in the literature studying adaptive NoCs [ 19 , 20 ] to improve application parallelism abilities and fast path NoCs [ 21 , 22 , 23 ], which improves latency and throughput by redesigning the PS routers. Adapt-NoC [ 20 ] introduces a reinforcement learning (RL)-based control policy.…”

Section: Related Workmentioning

confidence: 99%

“…Extra lanes are need for routers, which increases the design complexity of SoC. FastTrackNoC [ 23 ] presents a method of bypassing the VC switch traversal (ST) stage to reduce packet latency. It adds a fast-track path to a 2D mesh router between the head of a single input virtual channel (VC) buffer and its most used opposite output to reduce router processing time.…”

Section: Related Workmentioning

confidence: 99%

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PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

2023

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Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications. Network-on-chip (NoC) has become a very promising interconnection structure because of its good scalability, predictable interconnect length and delay, high bandwidth, and reusability. However, the most available packet routing NoC may not be the perfect solution for high-end heterogeneous multi-core real-time systems-on-chip (SoC) because of the excessive latency and cache cost overhead. Moreover, circuit switching is limited by the scale, connectivity flexibility, and excessive overhead of fully connected systems. To solve the above problems and to meet the need for low latency, high throughput, and flexibility, this paper proposes PCCNoC (Packet Connected Circuit NoC), a low-latency and low-overhead NoC based on both packet switching (setting-up circuit) and circuit switching (data transmission on circuit), which offers flexible routing and zero overhead of data transmission latency, making it suitable for high-end heterogeneous multi-core real-time SoC at various system scales. Compared with typically available packet switched NoC, our PCCoC sees 242% improved performance and 97% latency reduction while keeping the silicon cost relatively low.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

2023

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“…No recent publications about NoCs that are particularly aimed for MCPs have been found. For NoCs accommodated to CISCs, there are recent publications, such as FastTrackNoC [23] and FreewayNoC [24] which are compared to several state-of-the-art NoCs and found to be superior. Their area and energy consumption are much higher than those of the Bubble NoC, while the speeds are in the same order.…”

Section: B Detailed Comparisonmentioning

confidence: 99%

“…State-of-the-art for 14 nm VLSI technology is air-isolated wires with a capacitance of 0.15 fF/μm and a resistance of 2.7 Ω/μm [25], thereby providing a time constant of 0.405 fs/μm². The delay for the 150 μm wire in a Bubble NoC is 9.1 ps and applied to FastTrackNoC with 2.1 mm [23] wires it is 1.8 ns, and for FreewayNoC with 2.85 mm [24] wires it is 3.3 ns according to Spice. Some kind of sense amplifier is required to exceed the time constant.…”

Section: ) Wire Delaysmentioning

confidence: 99%

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Bubble NoC – A Low Energy Network-on-Chip with Small Footprint and High Performance

Carlstedt¹,

Rimborg²

2023

Preprint

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<div>The Bubble NoC is based on simplicity and provides outstanding performance. Flow control is implemented by <i>bubbles</i>, which are inserted between the flits. The logic resembles a traffic situation where a vehicle only moves if the next position is empty. When a flit moves, a bubble is created behind it, and when there is a blocking the bubbles are collapsed as the flits behind are packed together. Even when the Bubble NoC is saturated, it degrades gracefully, and the execution continues.</div><div> Deterministic prerouting is used, with the address stored as markers in a 2 out of 32 code. The routing algorithm shifts the address one step at each hop and turns or finishes when a marker starts the address.</div><div> The physical implementation is a mesh of <i>streets</i> containing duplex links of 38 wires carrying 32-bit payload. Signaling is based on current injection that charges the wires. A switch is placed in a four-way crossing, with a fifth local connection into a street. The switch contains input registers for each approaching street. Straight through traffic is simply passed on, and a diagonal gate is used for turning traffic.</div><div> All switches are bidirectional transmission gates, and the control is distributed as a sidewalk in a few µm of the periphery surrounding the intersection. In a 14 nm technology, the streets are 8 μm wide, the crossing is 17 μm in square, the hop frequency 6.67 GHz and the energy for a datapath 4.1 fJ/bit/hop (150 µm).</div>

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BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling

Strikos,

Ejaz,

Sourdis

2024

2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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FastTrackNoC: A NoC with FastTrack Router Datapaths

Cited by 3 publications

References 32 publications

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

Bubble NoC – A Low Energy Network-on-Chip with Small Footprint and High Performance

BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling

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