FAT-PIM: Low-Cost Error Detection for Processing-In-Memory

Abstract

Processing In Memory (PIM) accelerators are promising because they can provide massive parallelization and high efficiency in multiple application domains. These architectures can produce near-instantaneous results over wide data streams, allowing for real-time performance in data-intensive workloads. For instance, Resistive Memory (ReRAM) based PIM architectures are widely known for their inherent dot-product computation capability. While the performance of these architectures is appealing, reliability and accuracy are also important, especially in mission-critical real-time systems. Unfortunately, PIM architectures have a fundamental limitation in guaranteeing error-free operation. As a result, the current methods must pay high implementation costs or performance penalties to achieve reliable execution in the PIM accelerator. In this paper, we make a fundamental observation of this reliability limitation of ReRAM based PIM architecture. Accordingly, we propose a novel solution-Fault Tolerant PIM or FAT-PIM, that allows for low-cost error detection. Our evaluation using simulation technique shows that we can detect all errors with only 4.9% performance cost and 3.9% storage overhead.