Fault Modeling and Worst-Case Test Vectors for Leakage Current Failures Induced by Total Dose in ASICs

Worst-case test vectors of sequential ASiCS exposed to total dose

“…In this methodology, we target both logic failures and leakage current failures induced by total dose. This methodology depends on the cell-level fault models we developed in previous effort for both total dose induced logic and leakage current failures [1]- [4]. The block diagram in Figure 1 represents an example for a cycle-free sequential Worst-Case Test Vectors of Sequential ASICs Exposed to Total Dose Ahmed A. Abou-Auf, Mostafa M. Abdel-Aziz, Hamzah A. Abdel-Aziz and Amr G. Wassal T circuit is a 4-stage pipelined 5x5 multiplier where every stage has a combinational circuit followed by a register.…”

“…We previously introduced a methodology for identifying worstcase test vectors for combinational circuits in ASIC devices using cell-level fault model for leakage current failure [4]. In this methodology we employed the use of genetic algorithm to identify worst-case test vectors in within a reasonable search time.…”

“…The search space for worst case test vectors is , where n is the number of primary inputs of the circuit under test. In recent work, we improve the recent methodologies to make it valid for combinational circuits of ASIC devices with large numbers of gates and/or large numbers of input vectors and process in reasonable time faster than the exhaustive search method [4]. This was achieved by developing a search algorithm based on the concepts of genetic algorithms (GA).…”