Fault simulation of parametric bridging faults in CMOS IC's

Dalpasso, M.; Favalli, M.; Olivo, P.; Riccò, B.

doi:10.1109/43.240087

Cited by 22 publications

(10 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Several studies have observed that the voltage on the bridged nets depends on the resistance [103,104] as shown in Figure 2.3. For the example in Figure 2.2, the graphs in Figure 2.3 show how the voltages VA and VB on the bridged nets depend on the bridge resistance R sh .…”

Section: Models That Consider the Bridge Resistancementioning

confidence: 99%

Section: Models That Consider the Bridge Resistancementioning

confidence: 99%

“…a model for resistive bridging faults) associates a range of bridge resistances to each logic fault, as was considered in [103]. The fault model in [103] is called the parametric bridging fault model because it uses resistance as a parameter. The study in [103] was based on the assumption that all involved gates have the same logic threshold voltage T h, equal to half the voltage of Logic-1.…”

Section: Models That Consider the Bridge Resistancementioning

confidence: 99%

“…The fault model in [103] is called the parametric bridging fault model because it uses resistance as a parameter. The study in [103] was based on the assumption that all involved gates have the same logic threshold voltage T h, equal to half the voltage of Logic-1. With this assumption, there is only one resistance interval of faulty behaviour to consider, which is from R sh = 0Ω to R sh = R crit , from the lowest to the highest resistance value that can cause malfunction.…”

Section: Models That Consider the Bridge Resistancementioning

confidence: 99%

See 3 more Smart Citations

Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

View full text Add to dashboard Cite

The final part studies the impact of process variation on the behaviour of bridge defects.Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation.

show abstract

Section: Models That Consider the Bridge Resistancementioning

confidence: 99%

Section: Models That Consider the Bridge Resistancementioning

confidence: 99%

Section: Models That Consider the Bridge Resistancementioning

confidence: 99%

Section: Models That Consider the Bridge Resistancementioning

confidence: 99%

See 2 more Smart Citations

Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

View full text Add to dashboard Cite

show abstract

“…There are efforts to model fault propagation and effect [5,7,12,17,19,22,23,27,28,30,32,36,38,39,40,41,44,45,47,50,52]. Coverage is a popular topic, and the meaning of coverage can vary from simple detection to complete system recovery and reconfiguration [1,2,3,4,5,10,11,12,15,16,17,18,20,21,27,29,31,33,36,37,38,39,40,41,42,43,44,54,55]. There are papers about the efficient estimation of coverage [15,…”

Section: Literature Surveymentioning

confidence: 99%

Designing fault-injection experiments for the reliability of embedded systems

White

2012

2012 IEEE/AIAA 31st Digital Avionics Systems Conference (DASC)

View full text Add to dashboard Cite

This paper considers the long-standing problem of conducting fault-injections experiments to establish the ultra-reliability of embedded systems. There have been extensive efforts in fault injection, and this paper offers a partial summary of the efforts, but these previous efforts have focused on realism and efficiency. Fault injections have been used to examine diagnostics and to test algorithms, but the literature does not contain any framework that says how to conduct fault-injection experiments to establish ultra-reliability. A solution to this problem integrates field-data, arguments-from-design, and fault-injection into a seamless whole. The solution in this paper is to derive a model reduction theorem for a class of semi-Markov models suitable for describing ultra-reliable embedded systems. The derivation shows that a tight upper bound on the probability of system failure can be obtained using only the means of system-recovery times, thus reducing the experimental effort to estimating a reasonable number of easily-observed parameters. The paper includes an example of a system subject to both permanent and transient faults. There is a discussion of integrating fault-injection with fielddata and arguments-from-design.

show abstract

Interaction Testing in an Embedded System Using Hardware Fault Injection and Program Mutation

Sung

Choi

2004

Formal Approaches to Software Testing

View full text Add to dashboard Cite

Fault simulation of parametric bridging faults in CMOS IC's

Cited by 22 publications

References 16 publications

Investigation into voltage and process variation-aware manufacturing test

Investigation into voltage and process variation-aware manufacturing test

Designing fault-injection experiments for the reliability of embedded systems

Interaction Testing in an Embedded System Using Hardware Fault Injection and Program Mutation

Contact Info

Product

Resources

About