Fault Tolerance in Opto-electronic Computing.

Abstract

We have been quite successful in getting our work known to the community in the past few months. Specifically, in the several conferences we participated, people have shown great interests. . • A. Fault Modeling and Testing of Complex SystemsThis project has gotten some recognition in both fault modeling and testing of optical interconnects in a opto-electronic system. In the first part, we want to develop a new rma methodology for performance analysis of opto-electronic systems at a higher level. Our = * approach is to first identify possible failures in such interconnect implementations, and then 0) ___ extract information from the physical configuration and relate to the system performance parameters. In this way, system-level performance degradation can be estimated to construct design constraint for physical systems. One analysis on link failures in free-space optical interconnects is published in the Proceedings of the SPIE 94, January conference (Exhibit I). ) *,.: In the second part on testing, we proposed an architecture which integrates the concept of concurrency and distributed test pattern generation for testing complex circuits on a planer layout. This approach p-fo'tps test pattern generation and response analysis concurrently, Computers, vol. 10, no.4,..Circuits are partitioned into segments which can be tested in parallel in testing time bounded by 2An clock cycles, where n is the maximum no. of inputs for the biggest cluster. The result of this study will appear in 1994 Custom Integrated Circuits Conference (Exhibit III). Further hardware reduction can be reduced by binding test circuitry to functional units through logic synthesis and optimization algorithms. We are currently evaluating the impact of test pattern generation issue for the proposed architecture, and the result has been accepted to the 1994 International Conference of ASIC. Simulations are also underway on various benchmark circuit to better observe its overall performance on realistic systems. B.. Performance Evaluation of Fault Tolerant Optical Multi-stage Interconnection NetworkThis project helps to sc., up an evaluation scheme for complex degradable system. We think the uncertainty of optical interconnects supporting fault tolerance can easily be modeled in this framework. An event-driven simulator has been developed to study the corresponding measures as the replicated or dilated banyans degrade under component failure. A faultinjector is used to inject faults under some given distribution and to degrade the network accordingly. In the multipath MINs, different components are given different MTTF for a 4-replicated banyan of size 64 x 64 implemented with 2 x 2 switches. In practice, this can reflect a 64 processor 64 module shared memory multiprocessor environment (one of a moderate size), with exactly four distinct paths between any PE-MM pair. A set of design parameters needs be identified at the system level (as opposed to the device level), that can be used to tune up the system behavior to reflect upon the possible e...