2016
DOI: 10.7763/ijcte.2016.v8.1045
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Feasibility Test of Protocol Engines for a New Video System in Packet Communication

Abstract: Abstract-The layout between the processor and memory in parallel bus is very complex and difficult to place and route. The expansion of memory capacity and bandwidth is limited. A new memory system using an optical connection is proposed. We designed a serial interface using packet communication, and implemented a protocol engine to be executed on the interface. To test the feasibility of the protocol engine, we implemented a video system using an embedded processor on FPGA. The master and slave protocol engin… Show more

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