Field effect diode for effective CDM ESD protection in 45 nm SOI technology

Cao, Shuqing; Beebe, S.; Salman, Akram; Pelella, M.M.; Chun, Jung-Hoon; Dutton, R.W.

doi:10.1109/irps.2009.5173316

Cited by 14 publications

(7 citation statements)

References 24 publications

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“…Here, the p-n junctions sandwiched between the anode and the cathode are gate-induced, rather than built-in (doped-in), and thus, there is no need for precise control of the film doping profile, and the nearly intrinsic SOI film has higher carrier lifetime, and improves the state 1 retention (i.e., t rest ). Although a somewhat relaxed geometry FED was used here for proof of concept purposes, our previous results [10], [11], [17] suggest that it should be possible to design FED memory cells of superior scalability and performance: the gap length between gates G1 and G2 can be shrunk down to the technological limit without affecting the FED properties very much [18]. In fact, it is possible to push scaling even further (down to the 20-nm node according to our simulations [19]) using advanced FEDs, such as double-gate (DG), gate-all-around (GAA), and other multigate (MuG) structures, where the gate control of the channel is stronger.…”

Section: Discussionmentioning

confidence: 99%

SOI FED-SRAM Cell: Structure and Operation

Badwan

Chbili

et al. 2015

IEEE Trans. Electron Devices

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A static memory cell (SRAM) based on the field-effect diode (FED) is presented, and its operation is explained with the help of numerical device simulations. Although this new cell resembles the thin-capacitively coupledthyristor (TCCT) SRAM cell in concept and operation, it is nevertheless characterized by significant advantages. These advantages derive from the fact that the thyristorlike mode of operation of the FED is gate induced, whereas the TCCT is an actual built-in thyristor. The operation of the cell is explained with the help of suitable timing diagrams, and the mechanisms of storing 1 and 0 are analyzed with detailed numerical simulations. In one operation scheme (where the cell could better be termed quasi-SRAM), a sequence of restore pulses is periodically applied after the cell is put on Hold, which ensures that the stored data remain valid for as long as the cell is powered ON. High read 0/1 current margin, fast write/read time, and densely packed cells are among the cell advantages obtained.Index Terms-SOI, Field-effect diode (FED), SRAM, thin-capacitively coupled thyristor (TCCT), thyristor.

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Section: Discussionmentioning

confidence: 99%

SOI FED-SRAM Cell: Structure and Operation

Badwan

Chbili

et al. 2015

IEEE Trans. Electron Devices

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“…We have shown that field-effect diodes (FEDs) have superior characteristics over silicon-on-insulator metal-oxide-semiconductor field-effect transistors (SOI-MOSFETs) due to suppressed short-channel effects [2]- [4]. FEDs have been used for electrostatic-discharge protection [5]- [7] and memory-cell applications [8], [9].…”

Section: Performance Assessment Of Nanoscalementioning

confidence: 99%

Performance Assessment of Nanoscale Field-Effect Diodes

Manavizadeh

Raissi

Soleimani

et al. 2011

IEEE Trans. Electron Devices

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We propose a new structure called a side-contacted field-effect diode (FED). The fabrication of this new structure is simple, and it offers good electrical characteristics. Furthermore, a comprehensive analysis of FEDs is presented. The effect of heavydoping-induced band-gap narrowing on the performance of FEDs is investigated. Our results show that the calculated I on /I off ratio is at least two orders of magnitude larger than that obtained from models neglecting this effect. The figures of merit including intrinsic gate delay time, the energy-delay product, and the subthreshold slope have been studied. Our numerical investigations of the scaling of FEDs indicate that, in the nanometer regime, FEDs have a higher I on /I off ratio. The results demonstrate that FEDs are interesting candidates for future logic applications. Index Terms-Band gap narrowing, double gate, field effect diode (FED), nano transistor, short channel effects, side-contacted.

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“…3) and the field-effect diode (FED) (Fig. 4) were developed [23][24][25] based on the structures proposed in [26][27][28]. These devices combine the features of a P-N-P-N SCR to block leakage current during normal operating conditions, with a forward-biased P-N junction diode to shunt high current rapidly during ESD.…”

Section: Scr Structurementioning

confidence: 99%