Fine-grain reconfigurable logic cells based on double-gate CNTFETs

Jabeur, Kotb; Yakymets, Nataliya; O’Connor, Ian; Le-Beux, Sébastien

doi:10.1145/1973009.1973014

Cited by 16 publications

(6 citation statements)

References 6 publications

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“…To summarize, it seems that the new cell (POS-DRLC) furnish better results compared to the reconfigurable dynamic cells presented in previous works [7] [12] [13]. Furthermore, it offered the possibility to derive a static logic cell (CSL-DRLC) which showed an equal or better PDP compared to conventional 16nm-CMOS reconfigurable static logic cells regardless of the doubled number of configuration points required.…”

Section: Discussionmentioning

confidence: 78%

“…The ability to select the polarity (p-or n-type) in field by using a second back-gate, polarity gate [7] [9] [10] [11], has inspired Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.…”

Section: Device Characteristicsmentioning

confidence: 99%

“…Here, reconfigurability is enabled by modulating the transistor threshold voltages via the back gates. Second, the ambipolarity behaviour of DG-CNTFETs has been exploited to construct logic cells with various logic styles [6] [7]. Also, other design teams studied the impact of such reconfigurable cells at the architectural level [8] [9][10] [11] and showed that in addition to improved speed, power and area these new structures offer regularity, symmetry and especially provide the in-field reconfigurability.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Ambipolar double gate CNTFETs based reconfigurable logic cells

Jabeur

O’Connor

Beux

et al. 2012

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures

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This paper presents 2-input cells designed to perform reconfigurable operations in nanometric systems exploiting the ambipolar property of double-gate (DG) carbon nanotube (CNT) FETs. Previous work [12] described a dynamic logic cell generating only 14 functions instead of 16 normally performed by the multiplexer-based logic part of a CLB (Configurable Logic Block) of an FPGA for 2-inputs.In this work, a reconfigurable 2-input dynamic logic cell designed using DG-CNTFET devices is able to achieve a more complete set of functions by exploiting sum of products (SOP) and product of sums (POS) to express logic functions. We also demonstrated that a static logic version can be derived from this dynamic cell. Simulations reveal improvement factor of 3X in terms of delay and 23% of decrease in power consumption compared with the previous work [12]. When compared with 16nm-CMOS Technology, DG-CNTFET cells (dynamic logic and static logic style) showed a comparable PDP with a slight increase in area.

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Section: Discussionmentioning

confidence: 78%

Section: Device Characteristicsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Ambipolar double gate CNTFETs based reconfigurable logic cells

Jabeur

O’Connor

Beux

et al. 2012

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures

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“…Jabeur et al [25] proposed two 2-input cells designed to perform reconfigurable operations by exploiting the ambipolar property of double-gate CNTFETs. One of the cells is called SRC (Static Reconfigurable Cell) while the other is DRC (Dynamic/Domino Reconfigurable Cell).…”

Section: A Logic Cells Based On Reconfigurable Cntfetsmentioning

confidence: 99%

A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies

et al. 2021

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The functional component for an FPGA is the logic element which enables it to adapt to various hardware descriptions. This behavior is mostly due to the MUX-like functional flexibility provided by these logic elements or cells. However, in recent years, decelerating transistor sizing as per Moore's law has led to diminishing power, area and delay returns over cost [22]. Hence, the idea of venturing into FPGA logic cell designs based on emerging technologies is becoming not merely attractive, but even inescapable. The present work surveys various conventional and non-conventional logic cell designs proposed in the literature by identifying four logic design families, namely LUT-based, cone-based, matrix/cluster-based and transistor array-based. We then carry out a detailed comparison at two levels -a quantitative comparison based on metrics like power, delay and area which govern the overall performance of various FPGA architectures and secondly a qualitative comparison on factors which are important considering the ease of mainstream adoption. We highlight the importance of introducing and co-optimizing novel devices and architectures to maximize the overall FPGA performance.

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“…[18], silicon nanowires [19][20][21], organic single crystals [22] and organic semiconductor heterostructures [23]; carriers can be either electrons or holes, thus demonstrating a superposition of n-and ptype channel behavior. In a dual-gate FET context this property leads to the ability to examine new circuit design facilities with promising levels of compactness, regularity and reconfigurability [24][25][26][27]. While this work is expected to be valid for any ambipolar DGFET, we chose to validate and evaluate our proposal with a DG-CNTFET.…”

Section: Introductionmentioning

confidence: 99%

Low-power design technique with ambipolar double gate devices

Jabeur

O’Connor

Navarro

et al. 2012

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures

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Ambipolar FETs with channels composed of carbon nanotubes, graphene or undoped silicon nanowires have a V ds -dependent I off , a source of high leakage, as well as a low V TH , a source of high dynamic power. In this paper, we propose a circuit design technique to solve these issues for low-power logic circuits with ambipolar double-gate transistors, using the in-field controllability via the fourth device terminal. The approach is demonstrated for the complementary static logic design style. It dynamically lowers the dynamic power (short-circuit and capacitive) during the active mode and the static power during the inactive mode. We apply this approach in a simulation-based case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology. Compared to conventional structures, an average improvement of 3X in total power consumption was observed, with a decrease by a factor of 4X in short circuit power, and of 100X in static power (during the standby mode).

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Fine-grain reconfigurable logic cells based on double-gate CNTFETs

Cited by 16 publications

References 6 publications

Ambipolar double gate CNTFETs based reconfigurable logic cells

Ambipolar double gate CNTFETs based reconfigurable logic cells

A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies

Low-power design technique with ambipolar double gate devices

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