Fixed-point filter design and Riemannian geometry

Methodologies for Implementing FPGA-Based Control Systems

“…Consequently, the FPGA designer must determine the wordlength and radix setting of input, intermediate, and output signals in a design implementation to ensure the fidelity of the algorithm. A number of "automatic" conversion tools are becoming readily available to assist with such process, Cerna et al [2008]. In this paper, the FXP notation <e, wl, iwl> will be adopted, where e specifies the binary encoding (signed or unsigned), wl specifies the word-length total number of bits, and iwl specifies the number of bits allocated for the integer part.…”