Flexible FPGA-Based Architectures for Curve Point Multiplication over GF(p)

Amiet, Dorian; Curiger, Andreas; Zbinden, Paul

doi:10.1109/dsd.2016.70

Cited by 35 publications

(25 citation statements)

References 18 publications

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“…Table 4 presents the comparison of our method to the other two proposals on unified architecture. As shown, it can be inferred that our approach is notably faster than other similar works of [ 40 , 41 ].…”

Section: Hardware Implementation Results and Discussionmentioning

confidence: 53%

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Awaludin

Larasati

Kim

2021

Sensors

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In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

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Section: Hardware Implementation Results and Discussionmentioning

confidence: 53%

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Awaludin

Larasati

Kim

2021

Sensors

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show abstract

“…Table 4 presents the comparison 493 of our method to the other two proposals on unified architecture. As shown, it can be 494 inferred that our approach is notably faster than other similar works of [38,39].…”

mentioning

confidence: 69%

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Awaludin¹,

Larasati²,

Kim³

2021

Preprint

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In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes DSP primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020, yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

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“…Table III reports results for recent efficient multipliers, with generic primes, from the state of the art (see Sec. II): MA16 we reimplemented from [19] (on all FPGAs), MR8/16 from [26] (on A7 for Artix-7), AM32/64 multipliers from [21] (on V7), and MO64 multiplier from [20] (on V5). We also report the recent, very small, multipliers MAS1/2 from [27] on IGLOO 2 (I2) but we do not have this FPGA for comparison.…”

Section: Discussion and Comparisonsmentioning

confidence: 99%

“…In [21], a modified IDDMM was proposed on Virtex 7. For comparisons, we use their results for 256-bit multipliers with 32-bit (denoted AM32) and 64-bit (AM64) internal datapaths.…”

Section: State Of the Art In Modular Multiplicationmentioning

confidence: 99%

Generation of Finely-Pipelined GF(P) Multipliers for Flexible Curve Based Cryptography on FPGAs

Gallin

Tisserand²

2019

IEEE Trans. Comput.

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In this paper, we present modular multipliers for hardware implementations of (hyper)-elliptic curve cryptography on FPGAs. The prime modulus P is generic and can be configured at run-time to provide flexible circuits. A finelypipelined architecture is proposed for overlapping the partial products and reductions steps in the pipeline of hardwired DSP slices. For instance, 2, 3, or 4 independent multiplications can share the hardware resources at the same time to overlap internal latencies. We designed a tool, distributed as open source, for generating VHDL codes with various parameters: width of operands, number of logical multipliers per physical one, speed or area optimization, possible use of BRAMs, target FPGA. Our modular multipliers lead to, at least, 2 times faster as well as 2 times smaller circuits than state of the art operators.

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Flexible FPGA-Based Architectures for Curve Point Multiplication over GF(p)

Cited by 35 publications

References 18 publications

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Generation of Finely-Pipelined GF(P) Multipliers for Flexible Curve Based Cryptography on FPGAs

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