Formal Probabilistic Timing Verification in RTL

Error Estimation and Error Reduction With Input-Vector Profiling for Timing Speculation in Digital Circuits

“…There are researches like [13] and [14] who have studied the circuit behavior curve under input workload.…”

“…The circuit's dynamic stabilization curve will be affected by many types of variations, but the curve's basic shape is decided by the input workload. A rigorous analysis of path activation probability, which describes the typical dynamic behavior of 14" application [14]. Figure 3 shows an example of dynamic behavior, where A and B are two logic paths of a circuit with the same static delay time.…”

“…Wan and Chen [14] also proposed a method to analyze circuit-level dynamic behavior with a new data structure, called timed ternary decision diagrams (tTDDs). The tTDD is created based on the TDD, which is similar to binary decision diagrams (BDDs) [20] with the difference that each node has three possible outgoing branches, as discussed by Sasao [21].…”