Formal Specification and Verification of Few Combined Fragments of UML Sequence Diagram

Zafar, Nazir Ahmad

doi:10.1007/s13369-015-1999-9

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2020

2022

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“…The transformation of MARTE sequence diagrams to formal specifications, for the formal verification, has been investigated in several approaches like [46,47,48,49,50,51], but a few approaches as [12,52,53] have taken into consideration time specification in the transformation process. Previous works just deal with the flowing of events in sequence diagrams with implicit expression of time and consider only interleaving semantics.…”

Section: Discussion and Related Workmentioning

confidence: 99%

Formal Verification of UML MARTE Specifications Based on a True Concurrency Real Time Model

Chabbat

Saïdouni

Boukharrou

et al. 2020

cai

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For critical embedded systems the formal validation and verification is required. However, the real-time model checking suffers from problems of statespace explosion and clock explosion. The aim of this paper is to ensure an improvement of the Modeling and Analysis of Real-Time Embedded systems (MARTE), which is de facto standard, with formal semantics for verification finality. Therefore, we propose an operational method for translating UML sequence diagrams with MARTE annotations to Time Petri nets with Action Duration specifications (DTPN). Based on true concurrency semantics, the semantics of these specifications are defined in terms of Duration Action Timed Automata (daTA).

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