Formal verification of pulse-mode asynchronous circuits

Abstract

Abstract This paper addresses the problem of verifying pulse-mode asynchronous circuits, which combine advantages of different asynchronous design styles. A novel technique is proposed for constructing in a modular manner specifications and functional models of pulse-mode circuits. Case studies show the feasibility of formal verification on the basis of the proposed construction, integrated into an existing technique for verifying asynchronous circuits under relative timing constraints at several levels of abstraction.

Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems on Chip

“…In subsection 2.2., we briefly overview the active-edge specifications introduced in [7] and [13], which are used here to simplify the specification of control signals. In subsection 2.3, we briefly overview the asynchronous data communication schemes from [9] that are used in our verification case study.…”

“…For example, as illustrated in [13], the role of the clock signal in an edge-triggered flip-flop can be described by an active-edge specification. We refer to [13] on how to build active-edge specification by a "semihiding" operation, and to both [7] and [13] on how to reconstruct full specifications from active-edge specifications.…”

“…6, only the active edges of the clock signals are represented. Further, we transform the active-edge signals into transition-event signals using the procedures from [7] and [13]. The result of these transformations is the full specification of signal transitions shown in Fig.…”

“…Accordingly, a D flip-flop model is included to the data path in our asynchronous wrapper model and validity event data can be obtained at the output of D flip-flop. To describe the edge-triggered components (T, D), as well as the latch component, we use the active-edge specification models of [7] and [13]. For the lowest-level equations in Fig.…”