Forward and Reverse Biasing in Resistive Memories for Fast, Disturb-Free Read, and Verify

Abstract

The potential of resistive random access memory (ReRAM) to provide high speed operation is held back by the need to verify during set/reset, and sensitivity to read disturb. 50 nm HfO2 cells are measured for disturb in forward and reverse directions, and at 25 and 85 °C. Two circuit proposals provide speed and reliability improvement. First, bipolar verify reduces write time. If the verify direction matches the set/reset direction, read voltage can be increased, which reduces signal development time, and eliminates the need to switch the highly capacitive source line voltage. Secondly, reverse read with dynamic write-back provides fast, disturb-free read. A margin-check is performed in parallel to normal reverse-read. Disturb of the low resistance state is monitored, and then, if needed, set write-back occurs. Based on disturb data, write-back occurs infrequently, after ∼5×109 reads. By these two proposals, write time can be reduced by 3× and 5× faster read with disturb immunity can be achieved.