FPGA based disparity map computation with vergence control

Microprocessors and Microsystems

Aguilar-González

Arias-Estrada

et al. 2016

International audienceThe stereo matching is one of the most widely used algorithms in real-time image processing applications such as positioning systems for mobile robots, three-dimensional building mapping and both recognition, detection and three-dimensional reconstruction of objects. In order to improve the runtime, stereo matching algorithms often have been implemented in dedicated hardware such as FPGA or GPU devices. In this article an FPGA stereo matching unit based on fuzzy logic is described. The proposed method consists of three stages: first, three similarity parameters inherent to each pixel contained in the input stereo pair are determined; later, these parameters are submitted to a fuzzy inference system that determines a value of fuzzy-similarity; finally, the disparity value is determined as the index for the maximum value of the fuzzy-similarity values (zero up to d max). Dense disparity maps are computed at a rate of 76 frames per second for input stereo pairs of 1280x1024 pixel resolution and a maximum expected disparity equal to 15. The developed FPGA architecture provides reduction of the hardware resource demand; up to 67,384, minimum 9,788 for logic units, up to 35,475, minimum 11,766 for bits of memory. Increases the processing speed; up to 78,725,120, minimum 14,417,920 pixels per second and outperforms the accuracy level of most of real-time stereo matching algorithms reported in the literature

Section: Discussion and Analysis Of Resultsmentioning

confidence: 96%

An FPGA stereo matching unit based on fuzzy logic

Microprocessors and Microsystems

Aguilar-González

Arias-Estrada

et al. 2016

“…In [9], one module for real-time disparity maps computation implemented in an FPGA Stratix IV of Altera is proposed; disparity maps are computed at a rate of 320 frames per second for images of 640 Â 480 pixels and a maximum expected disparity equal to 80. Finally, the module developed in [11] enables to process 275 frames per second for images with a maximum expected disparity equal to 80 and 640 Â 480 pixel resolution; the presented architecture provides a high speed of processing at expenses of the accuracy with great scalability in terms of disparity levels.…”

Section: Related Workmentioning

confidence: 99%

FPGA implementation of an efficient similarity-based adaptive window algorithm for real-time stereo matching

Aguilar-González²

2015

J Real-Time Image Proc

International audienceThe stereo matching is one of the most widely used algorithms in real-time image processing applications such as positioning systems for mobile robots, three-dimensional building mapping and both recognition, detection and three-dimensional reconstruction of objects. In area-based algorithms, the similarity between one pixel of the left image and one pixel of the right image is measured using a correlation index computed on vicinities of these pixels called correlation windows. In order to preserve edges, small windows need to be used. On the other hand, for homogeneous areas, large windows are required. Due to only local information is used, matching between primitives is difficult. In this article, FPGA implementing of an efficient similarity-based adaptive window algorithm for dense disparity maps estimation in real-time is described. In order to evaluate the proposed algorithm behavior, the developed FPGA architecture was simulated via ModelSim-Altera 6.6c using different synthetic stereo pairs and different sizes for correlation window. In addition, the FPGA architecture was implemented in an FPGA Cyclone IIEP2C35F672C6 embedded in an Altera development board DE2. The disparity maps are computed at a rate of 76 frames per second for stereo pairs of 1280×1024 pixel resolution and a maximum expected disparity equal to 15. The developed FPGA architecture offers better results with respect to the most of real-time area-based stereo matching algorithms reported in the literature, allows increasing the processing speed up to 93,061,120 pixels per second and enables it to be implemented in the majority of the medium-gamma FPGA devices

“…In this figure a high improvement in regions of uniform texture and a low improvement in the points near the edges is obtained. The proposed method requires less computational load in contrast to various methods in the reported literature [7], [8], [15], [16], however compute a disparity map for a stereo pair of 384x288 pixel resolution (Tsukuba scene resolution) implies a runtime close to 1 second. These runtime values are not acceptable for real-time applications.…”

Section: Compositionmentioning

confidence: 99%

“…This method processes images up to 640x480 pixel resolution at a rate of 30 frames/s and produces 8-bit dense disparity maps within a range of disparities up to 128 pixels. In [16] a module for calculating the real-time disparity map is proposed. The module was implemented in a single FPGA of Altera Stratix IV family.…”

Section: Introductionmentioning

confidence: 99%

An FPGA Correlation-Edge Distance approach for disparity map

Aguilar-González

2015 International Conference on Electronics, Communications and Computers (CONIELECOMP)

Arias-Estrada

et al. 2015

International audience—This paper describes an FPGA Correlation-Edge Distance approach for real time disparity map generation in stereo-vision. The proposed method calculates the disparity map for the input and disparity map for Edge Distance images of a stereopair. In both cases the approximation algorithm of disparity map SAD (Sum of Absolute Differences) is used. The final disparity map is determined from the previously generated maps, considering a homogeneity parameter defined for each point in the scene. Due to low complexity when implementing stereo-vision algorithms in FPGA devices, the proposed method was implemented in a Cyclone II EP2C35F672C6 FPGA assembled in an Altera DE2 breadboard. The developed module can process stereo-pairs of 1280×1024 pixel resolution at a rate of 75 frames/s and produces 8-bit dense disparity maps within a range of disparities up to 63 pixels. The presented architecture provides a significant improvement in regions with uniformed texture over correlation based stereo-vision algorithms in the reported literature and an accelerated processing rate