FPGA based implementation of FAST and BRIEF algorithm for object recognition

Heo, Hoon; Lee, Jung-yong; Lee, Kwang-Yeob; Lee, Chanho

doi:10.1109/tencon.2013.6718842

Cited by 19 publications

(27 citation statements)

References 5 publications

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“…For contrast, our system and previous works are listed in Table 2. Those works in [14,[20][21][22][23] only support monocular cameras. Although our system is targeted to binocular vision, performance metrics of monocular version of our system is also given.…”

Section: Performance Analysismentioning

confidence: 99%

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FPGA-based Binocular Image Feature Extraction and Matching System

Wang

Zhao

et al. 2019

Proceedings of the 2019 4th International Conference on Multimedia Systems and Signal Processing

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Image feature extraction and matching is a fundamental but computation intensive task in machine vision. This paper proposes a novel FPGA-based embedded system to accelerate feature extraction and matching. It implements SURF feature point detection and BRIEF feature descriptor construction and matching. For binocular stereo vision, feature matching includes both tracking matching and stereo matching, which simultaneously provide feature point correspondences and parallax information. Our system is evaluated on a ZYNQ XC7Z045 FPGA. The result demonstrates that it can process binocular video data at a high frame rate (640 × 480 @ 162fps). Moreover, an extensive test proves our system has robustness for image compression, blurring and illumination.

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Section: Performance Analysismentioning

confidence: 99%

“…For [20,21], only feature detection and description is accelerated on FPGA, while the matching of them are finished by software. So their frame rates are low Literatures [13,22,23] accelerate feature point extraction 、 descriptor construction and matching. The frame rates of [22,23] are still low.…”

Section: Performance Analysismentioning

confidence: 99%

FPGA-based Binocular Image Feature Extraction and Matching System

Wang

Zhao

et al. 2019

Proceedings of the 2019 4th International Conference on Multimedia Systems and Signal Processing

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“…Suzuki's work [13] and Rao's work [14] support to process 60 fps videos within 16 ms/frame. The process time of Heo's work [16] reaches 18 ms/frame, which is far away from the needs of a high frame rate and ultra-low delay system. As a result, the current existing works does not support to process 1000 fps videos within 1 ms/frame.…”

Section: Introductionmentioning

confidence: 97%

“…In recent years, several works [13]- [16] that try to accelerate the local feature based matching system by FPGA have been presented. So far, no work targets on the high frame rate and ultra-low delay matching system is found.…”

Section: Introductionmentioning

confidence: 99%

Pixel Selection and Intensity Directed Symmetry for High Frame Rate and Ultra-Low Delay Matching System

Ikenaga

2018

IEICE Trans. Inf. & Syst.

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High frame rate and ultra-low delay matching system plays an increasingly important role in human-machine interactive applications which call for higher frame rate and lower delay for a better experience. The large amount of processing data and the complex computation in a local feature based matching system, make it difficult to achieve a high process speed and ultra-low delay matching with limited resource. Aiming at a matching system with the process speed of more than 1000 fps and with the delay of less than 1 ms/frame, this paper puts forward a local binary feature based matching system with field-programmable gate array (FPGA). Pixel selection based 4-1-4 parallel matching and intensity directed symmetry are proposed for the implementation of this system. To design a basic framework with the high process speed and ultra-low delay using limited resource, pixel selection based 4-1-4 parallel matching is proposed, which makes it possible to use only one-thread resource consumption to achieve a four-thread processing. Assumes that the orientation of the keypoint will bisect the patch best and will point to the region with high intensity, intensity directed symmetry is proposed to calculate the keypoint orientation in a hardware friendly way, which is an important part for a rotation-robust matching system. Software experiment result shows that the proposed keypoint orientation calculation method achieves almost the same performance with the state-of-art intensity centroid orientation calculation method in a matching system. Hardware experiment result shows that the designed image process core supports to process VGA (640×480) videos at a process speed of 1306 fps and with a delay of 0.8083 ms/frame.

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“…In addition, some studies have explored the use of FPGA-SoCs to solve artificial vision tasks using embedded systems. In Heo et al, 18 an object recognition scheme implemented on an FPGA-SoC was developed. The algorithms used were FAST, BRIEF, and Hamming distance.…”

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confidence: 99%

FPGA‐SoC implementation of an ICA‐based background subtraction method

Carrizosa-Corral

Vázquez-Cervantes

Montes

et al. 2018

Circuit Theory & Apps

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SummaryThis paper presents the development and implementation of an independent component analysis (ICA)–based background subtraction method on a field programmable gate array (FPGA) system on a chip (SoC) with embedded processor. The use of the classic form of ICA for this purpose results in a complex implementation with high hardware resource usage for an embedded system. Therefore, an alternative version of FastICA was developed that adapts directly to the parallelism offered by the FPGA. In addition, the incorporation of this version of ICA into the motion‐detection method exploits the architecture of the FPGA‐SoC with embedded processor. This recent technology complements the parallelism of the FPGA with the general‐purpose computing capacity of the processors while maintaining low energy consumption and a compact size. The above features are appropriate for autonomous devices that handle mainly background subtraction, while a central device receives this information and performs the remaining tasks required for the application. The use of processors allows a faster implementation and integration of the device into other systems in a simple manner, while the parallelism of the FPGA increases the processing speed by accelerating intensive numeric calculations. The results obtained from the implementation that uses both FPGA and the embedded processor of the SoC show an increase of 3300% in the number of frames per second compared with an implementation that uses only the embedded processor.

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FPGA based implementation of FAST and BRIEF algorithm for object recognition

Cited by 19 publications

References 5 publications

FPGA-based Binocular Image Feature Extraction and Matching System

FPGA-based Binocular Image Feature Extraction and Matching System

Pixel Selection and Intensity Directed Symmetry for High Frame Rate and Ultra-Low Delay Matching System

FPGA‐SoC implementation of an ICA‐based background subtraction method

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