FPGA based pipelined architecture for RC5 encryption

Bevi, A. Ruhan; Sheshu, S. S. V.; Malarvizhi, S.

doi:10.1109/dictap.2012.6215353

Cited by 3 publications

(5 citation statements)

References 11 publications

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“…179 MHz and area is reduced 50% in comparision with work done by different devices. [2] The work results are in confirmity with the trend comparision of results published by other workers in various devices.…”

Section: Resultssupporting

confidence: 90%

“…The area-delay product has shown a reduction of nearly 50% when compared with the reference [2] of RC5 design. The simulation of the pipelined design is shown in the figure 8, which clearly illustrates the pipelining mechanism of the proposed model for 12 rounds and encrypted data is shown at output after every clock pulse after initial delay…”

Section: Implementation Resultsmentioning

confidence: 92%

“…In the proposed RC5 dedicated hardware, by introducing an architecture suitable for each operation used for the encryption, high speed processing, and area reduction can be realized. The high performance pipeline hardware proposed in [2] in which implementation of RC5 that improves the response time of the system with less resources and performance of this architecture provide high throughput. In [3] represents RC5 algorithm and its implementation for low power and in complex architecture.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of 64- bit RC5 Encryption Algorithm for Pipelined Architecture

Singh¹,

Gour²,

Soni³

2014

IJCA

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In modern days data transmission through a channel requires more security. Security based more important transmission is comparatively better & believable than simple transmission. The aim of this work to use RC5 algorithm for encryption and decryption of data for secure data transmission from one place to another place for proper communication purposes. Today this is utmost importance to send information confidentially through network without any risk for hackers or unauthorized possibility to access from the network. This urgently require security implementation devices in network for well secured transmission of data. Symmetric encryption cores provide data protection through the use of secret key only known as encryption, whereas decryption deals with the yield at the end of communication path. Today world require secure transmission through cryptographic algorithm. Keeping view in mind the proposed well defined RC5 architecture have been taken, based on the fact for suitability of each operation for encryption, high speed processing and possibility of area reduction. The work results of the study clearly indicate that logic implementation by this hardware is maximum clock frequency of 179 MHz and areas reduced to 50% as compare with the results of design of previous worker. The propose design is described in verilog, synthesized by Xilinx synthesis technology.

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Section: Resultssupporting

confidence: 90%

Section: Implementation Resultsmentioning

confidence: 92%

Section: Introductionmentioning

confidence: 99%

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Analysis of 64- bit RC5 Encryption Algorithm for Pipelined Architecture

Singh¹,

Gour²,

Soni³

2014

IJCA

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“…The future scope of this work will be where priority of the data has a given more emphasis with sliding window. Ruhan Bevil et al (2012) again presented FPGA based pipelined architecture for RC5 that improves response time of the system with less resources using H/CDFG technique [5]. H/CDFG is made of combination of different CDFG's and DFG's which describes the data flow and control transfer in the design, often used in many design approaches to reduce time to design .The proposed hardware implementation is more suitable for RC5 as it is achieve to response time and high throughput result will term on both of speed and security.…”

Section: Fig5: 2d-discrete Wavelet Transfrommentioning

confidence: 99%

“…[5] The drawback of this architecture is, since only one key is use the encrypt the data; it is easy to retrieve the intermediate result of any round through the pipeline. [1].…”

Section: Introductionmentioning

confidence: 99%

Survey on FPGA-based Pipelined Architecture for RC5 Encryption

Singh¹,

Gour²,

Soni³

2013

IJCA

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In current scenario, electronic devices handling confidential information. In these devices encryption algorithm proposed have been satisfy to protect the confidential information and known for their cryptographic applications. The extensively use of reconfigurable processor like FPGA for cryptographic application which have reduced the time to market of hardware logic. In this survey presented that the FPGA-based hardware architecture is best approach for high performance of circuit, it reduces the response time and resources. This hardware architecture work on Verilog as well as VHDL language.

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