FPGA based sliding window architecture for RC5 encryption

Bevi, A. Ruhan; Sheshu, S. S. V.; Malarvizhi, S.

doi:10.1145/2345396.2345496

Cited by 4 publications

(3 citation statements)

References 8 publications

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“…In 2012, Ruhan Bevil et al presented FPGA based Sliding Window Architecture for RC5 Encryption which reduces the waiting time by schedule using sliding window method [4]. The sliding window is a popular data link layer protocol widely used in data transmission methods and this architecture used in busy data traffic network.…”

Section: Fig5: 2d-discrete Wavelet Transfrommentioning

confidence: 99%

“…For RC5 cryptography and its implementation proposed a dedicated hardware [1] .In this proposed hardware, are introducing a new hardware-oriental algorithm into the shift round process during encryption and decryption, high-speed processing and area reduction were realized. Desisn a new architecture for RC5 algorithm in FPGA which reduces the waiting time by data schedule using the sliding window method [4].…”

Section: Introductionmentioning

confidence: 99%

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Survey on FPGA-based Pipelined Architecture for RC5 Encryption

Singh¹,

Gour²,

Soni³

2013

IJCA

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In current scenario, electronic devices handling confidential information. In these devices encryption algorithm proposed have been satisfy to protect the confidential information and known for their cryptographic applications. The extensively use of reconfigurable processor like FPGA for cryptographic application which have reduced the time to market of hardware logic. In this survey presented that the FPGA-based hardware architecture is best approach for high performance of circuit, it reduces the response time and resources. This hardware architecture work on Verilog as well as VHDL language.

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Section: Fig5: 2d-discrete Wavelet Transfrommentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Survey on FPGA-based Pipelined Architecture for RC5 Encryption

Singh¹,

Gour²,

Soni³

2013

IJCA

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“…The high performance pipeline hardware proposed in [2] in which implementation of RC5 that improves the response time of the system with less resources and performance of this architecture provide high throughput. In [3] represents RC5 algorithm and its implementation for low power and in complex architecture. Our work aim to design objective based pipeline architecture specifically based for low delay with high frequency.…”

Section: Introductionmentioning

confidence: 99%

Analysis of 64- bit RC5 Encryption Algorithm for Pipelined Architecture

Singh¹,

Gour²,

Soni³

2014

IJCA

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In modern days data transmission through a channel requires more security. Security based more important transmission is comparatively better & believable than simple transmission. The aim of this work to use RC5 algorithm for encryption and decryption of data for secure data transmission from one place to another place for proper communication purposes. Today this is utmost importance to send information confidentially through network without any risk for hackers or unauthorized possibility to access from the network. This urgently require security implementation devices in network for well secured transmission of data. Symmetric encryption cores provide data protection through the use of secret key only known as encryption, whereas decryption deals with the yield at the end of communication path. Today world require secure transmission through cryptographic algorithm. Keeping view in mind the proposed well defined RC5 architecture have been taken, based on the fact for suitability of each operation for encryption, high speed processing and possibility of area reduction. The work results of the study clearly indicate that logic implementation by this hardware is maximum clock frequency of 179 MHz and areas reduced to 50% as compare with the results of design of previous worker. The propose design is described in verilog, synthesized by Xilinx synthesis technology.

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