FPGA Design and Implementation of Low Power Consumption LDPC Encoder Based on DVB-S2

Design of Mobile DDR IO Standards Based Portable Devnagari Unicode Reader on FPGA

“…According to DVB-S2 standard for LDPC (Low Density Parity Check) codes, a novel LDPC codes encoder circuit structure is designed [5]. Due to the random nature of the input data, this structure significantly reduces the power consumption of the calculation circuit [5]. Using event-triggered radios is well suited and could lead to significant reduction of the overall power consumption of WSNs [6].…”

“…In [4], a hybrid software-hardware approach making use of a field-programmable gate array platform as a heat equation solver that can be easily attached to a PC using a PCI bus with the goal of obtaining a portable system to be used during field experiments. According to DVB-S2 standard for LDPC (Low Density Parity Check) codes, a novel LDPC codes encoder circuit structure is designed [5]. Due to the random nature of the input data, this structure significantly reduces the power consumption of the calculation circuit [5].…”

“…But, no research in Devnagari Unicode Reader(DUR) design has been conducted, which makes this research first of its kind. The aim of this paper is to fill this research gap and design a portable DUR as well as thermal efficient [12] and energy efficient [1,[4][5][6][7][8][9][10][11]. Thermal efficient DUR means that DUR is able to operate in the temperature range of 0 o C-125 o C. Energy efficient DUR means that DUR is able to run with the least amount of energy as compared to their traditional counterpart.…”