FPGA Design with Double-Gate Carbon Nanotube Transistors

Abstract

Double-gate carbon nanotube field effect transistors (DGCNTFETs) are novel devices showing an interesting property allowing to control the p-or n-type behavior during the device operation. This opens up the opportunity for novel design paradigms. Based on a compact physical model of these devices, we demonstrate the benefit of designing field-programmable gate arrays (FPGAs) using fine-grain DG-CNTFET logic blocs rather than traditional look-up tables and coarse-grain DG-CNTFET logic blocs. In particular, we show a reduction by 13% to 48% on average in terms of delay of FPGA benchmarks. IntroductionThe scaling down of complementary metal-oxide-semiconductor (CMOS) technology has led to the emergence of novel post-CMOS devices, such as carbon nanotubes (CNTs). One of the challenges of using CNT technology for building transistors is the chemical doping. Using undoped CNTs is possible, but it results in an ambipolar behavior of the carbon nanotube field effect transistors (CNTFETs), meaning that undoped CNTFETs conduct under both positive and negative gate bias. This issue is addressed using a second gate, which controls whether the device operates as p-or a n-type [1]. The polarity of double-gate (or dual-gate) CNTFETs (DG-CNTFETs) can be selected during operation time.This property offers the opportunity to design logic gates with reconfigurable devices, leading to more logic functions drawn on the same silicon area. We leverage this property by constructing a full reconfigurable logic system that is reminiscent of a fieldprogrammable gate array (FPGA). Reconfigurable circuits are gaining interest because of their low technology cost, fast design time and enhanced fault-tolerance compared to application-specific integrated circuits (ASICs) [2]. However, FPGAs necessitate a large number of configuration memories and have a higher cost in terms of area and power consumption compared to ASICs. Our approach to address these issues is to implement FPGAs using reconfigurable DG-CNTFET logic gates instead of look-up tables (LUTs) as basic logic elements (BLEs). Our BLEs require less configuration memory, and their design is area efficient.In order to assess the benefits of the proposed approach, we first build a family of basic logic elements with DG-CNTFETs, which we characterize using a compact model. , 34 (1) 1005-1010 (2011) 10.1149/1.3567706 We then evaluate the FPGA performance on a large application benchmark for different architecture scenarios. The same design flow is used with LUT-based FPGAs. We demonstrate that the proposed approach with fine-grain DG-CNTFET gates is 48% faster than coarse grains and 13% faster than LUTs. FPGAs with fine-grain DG-CNTFET gates have a cost in terms of area with respect to LUTs (10%), while they are 45% smaller than coarse-grain DG-CNTFET gates. ECS TransactionsThe paper is organized as follows. We first survey previous works dealing with DG-CNTFET technology. Then we introduce a compact physical model for the considered devices. Subsequently, we introduce the design of re...