2019
DOI: 10.3390/a12020028
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FPGA Implementation of ECT Digital System for Imaging Conductive Materials

Abstract: This paper presents the hardware implementation of a stand-alone Electrical Capacitance Tomography (ECT) system employing a Field Programmable Gate Array (FPGA). The image reconstruction algorithms of the ECT system demand intensive computation and fast processing of large number of measurements. The inner product of large vectors is the core of the majority of these algorithms. Therefore, a reconfigurable segmented parallel inner product architecture for the parallel matrix multiplication is proposed. In addi… Show more

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Cited by 6 publications
(7 citation statements)
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References 26 publications
(34 reference statements)
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“…In [66], a complete standalone 2D ECT system (16x16 frame size) using FPGA (Cyclone-V) was suggested. The system, which hosts the LBP algorithm, was designed for imaging lost foam coating process.…”
Section: A Recent Reviewmentioning
confidence: 99%
“…In [66], a complete standalone 2D ECT system (16x16 frame size) using FPGA (Cyclone-V) was suggested. The system, which hosts the LBP algorithm, was designed for imaging lost foam coating process.…”
Section: A Recent Reviewmentioning
confidence: 99%
“…The method generates double BCD (Binary-Coded Decimal) numbers using decimal multiples 2X, 4X, and 5X. The redundant decimal adder is used to reduce the generated 2n BCD partial products to a redundant number in the range of [0,15]. The final redundant product is then converted to BCD encoding.…”
Section: Related Workmentioning
confidence: 99%
“…Since the set of applications taking advantage of these specialized units is somehow limited, most processors only include some kind of specific instructions to help in the execution of decimal operations performed in software. In this scenario, FPGAs (Field Programmable Gate Array) may be a good alternative for the execution of decimal arithmetic with dedicated hardware modules, like in many other applications [14,15]. Many financial applications already use FPGAs to speed-up the execution of their algorithms and so an hardware reprogrammable platform is already available.…”
Section: Introductionmentioning
confidence: 99%
“…The FPGA realization of the matrix-vector multiplication algorithm has been tackled by many research work at the algorithmic level as well as at the bit-manipulation level [30][31][32]. Most of the FPGA implementation of these proposed parallel structure of the matrix multiplication at an algorithmic level are for small matrix dimensions.…”
Section: Introductionmentioning
confidence: 99%