FPGA Implementation of MAC Unit for Artificial Neural Network Accelerators

Alsayyab, Sabreen; Karkar, Ammar J.M

doi:10.1109/aest55805.2022.10413151

2022 2nd International Conference on Advances in Engineering Science and Technology (AEST) 2022

DOI: 10.1109/aest55805.2022.10413151

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FPGA Implementation of MAC Unit for Artificial Neural Network Accelerators

Sabreen Alsayyab,

Ammar J.M Karkar

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Cited by 3 publications

References 11 publications

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FPGA Implementation of Stochastic Approximate Multipliers for Neural Networks

Saravanan,

Dayana,

Rani

et al. 2024

2024 First International Conference on Electronics, Communication and Signal Processing (ICECSP)

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FPGA Implementation of Stochastic Approximate Multipliers for Neural Networks

Saravanan,

Dayana,

Rani

et al. 2024

2024 First International Conference on Electronics, Communication and Signal Processing (ICECSP)

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Design and Implementation of a Parameterized Elastic Deep Neural Network Accelerator with a 32-Bit Floating-Point Number Using FPGA

Alsultany,

Karkar

2023

2023 International Conference on Modeling &Amp;amp; E-Information Research, Artificial Learning and Digital Applications (ICMER

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Dynamic Precision Scaling in MAC Units for Energy-Efficient Computations in Deep Neural Network Accelerators

P C,

M R,

Gopi

et al. 2024

2024 28th International Symposium on VLSI Design and Test (VDAT)

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FPGA Implementation of MAC Unit for Artificial Neural Network Accelerators

Cited by 3 publications

References 11 publications

FPGA Implementation of Stochastic Approximate Multipliers for Neural Networks

FPGA Implementation of Stochastic Approximate Multipliers for Neural Networks

Design and Implementation of a Parameterized Elastic Deep Neural Network Accelerator with a 32-Bit Floating-Point Number Using FPGA

Dynamic Precision Scaling in MAC Units for Energy-Efficient Computations in Deep Neural Network Accelerators

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