FPGA implementation of neural network as processing element in ice detector

Marouf, Mohamed; Popovic-Bozovic, Jelena; Popović, Ivan

doi:10.1109/neurel.2012.6419970

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…In [14] the authors proposed a new hardware / software system for the implementation of ANN with two hidden layers. The first layer has three neurons and the second has two neurons, and an output layer has two neurons.…”

Section: Work Literature Reviewmentioning

confidence: 99%

Performance evaluation and implementations of MFCC, SVM and MLP algorithms in the FPGA board

Khamlich

Fathallah

Atouf

et al. 2021

Int. j. electr. comput. eng. syst. (Online)

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One of the most difficult speech recognition tasks is accurate recognition of human-to-human communication. Advances in deep learning over the last few years have produced major speech improvements in recognition on the representative Switch-board conversational corpus. Word error rates that just a few years ago were 14% have dropped to 8.0%, then 6.6% and most recently 5.8%, and are now believed to be within striking range of human performance. This raises two issues - what is human performance, and how far down can we still drive speech recognition error rates? The main objective of this article is the development of a comparative study of the performance of Automatic Speech Recognition (ASR) algorithms using a database made up of a set of signals created by female and male speakers of different ages. We will also develop techniques for the Software and Hardware implementation of these algorithms and test them in an embedded electronic card based on a reconfigurable circuit (Field Programmable Gate Array FPGA). We will present an analysis of the results of classifications for the best Support Vector Machine architectures (SVM) and Artificial Neural Networks of Multi-Layer Perceptron (MLP). Following our analysis, we created NIOSII processors and we tested their operations as well as their characteristics. The characteristics of each processor are specified in this article (cost, size, speed, power consumption and complexity). At the end of this work, we physically implemented the architecture of the Mel Frequency Cepstral Coefficients (MFCC) extraction algorithm as well as the classification algorithm that provided the best results.

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Section: Work Literature Reviewmentioning

confidence: 99%

Performance evaluation and implementations of MFCC, SVM and MLP algorithms in the FPGA board

Khamlich

Fathallah

Atouf

et al. 2021

Int. j. electr. comput. eng. syst. (Online)

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“…[Lozito et al 2014] implementa através de co-processadores uma RNA e acelera as operações de ponto flutuante com o FPGA. [Marouf et al 2012] monta e treina uma RNA para detecção de gelo utilizada em voos em baixas temperaturas ou até mesmo no tráfego em redes rodoviárias.…”

Section: Trabalhos Relacionadosunclassified

Arquitetura Adaptável para Execução de Redes Neurais Artificiais em Dispositivos FPGA

Castro

Heinen

Neves

2019

Anais Estendidos Do XX Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD Estendido 2019)

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Dentro do campo de Inteligências Artificiais, as Redes Neurais Artificiais (RNA) recebem destaque pela capacidade de aprender através de processos de treinamento e sua pluralidade de aplicações, que vão desde a classificação de padrões até o cálculo de funções. A implementação de algoritmos em hardware permite a paralelização de etapas e, então, a aceleração de processamento. Este trabalho propõe uma arquitetura de hardware de propósito geral para a execução de RNA em dispositivos FPGA. Implementada através da linguagem VHDL, a arquitetura proposta processa uma camada em média a cada 3 ciclos de clock. Simulada no dispositivo EP3C25F324C6, foi atingida a frequência de clock de 106.53 MHz e necessários 65.5 Kb de memória.

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FPGA implementation of neural network as processing element in ice detector

Cited by 2 publications

References 8 publications

Performance evaluation and implementations of MFCC, SVM and MLP algorithms in the FPGA board

Performance evaluation and implementations of MFCC, SVM and MLP algorithms in the FPGA board

Arquitetura Adaptável para Execução de Redes Neurais Artificiais em Dispositivos FPGA

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