FPGA implementation of proficient Vedic multiplier architecture using hybrid carry select adder

Thamizharasan, V.; Kasthuri, N.

doi:10.1080/00207217.2023.2245194

Cited by 3 publications

(2 citation statements)

References 16 publications

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“…The multipliers are categorized based on reduction of partial products. There are Array multiplication, Wallace multiplication, Bypassing multiplier, Booth multiplication, Vedic multiplication and Booth recorded Wallace tree multiplication, Baugh Wooley multiplication, Braun multiplication and etc., 12 .…”

Section: Review Of Multipliersmentioning

confidence: 99%

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

Thamizharasan,

Parthipan

2024

Sci Rep

Self Cite

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In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%).

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Section: Review Of Multipliersmentioning

confidence: 99%

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

Thamizharasan,

Parthipan

2024

Sci Rep

Self Cite

View full text Add to dashboard Cite

show abstract

“…The multipliers were categorized based on reduction of partial products. There are Array multiplication, Wallace multiplication, Bypassing multiplier, Booth multiplication, Vedic multiplication and Booth recorded Wallace tree multiplication, Baugh Wooley multiplication, Braun multiplication and etc., [12].…”

Section: Review Of Multiplicationmentioning

confidence: 99%

Design of Efficient Binary Multiplier Architecture using Hybrid Compressor with FPGA implementation

Thamizharasan,

Parthipan

2023

Preprint

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In emerging digital world, the high-performance arithmetic computing module with low power and reduced area are required to compute the Signal processing application operations. In that signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and arithmetic & logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplication and it used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor for application of Cryptography and signal processing system. The proposed hybrid compressor-based multiplier is designed and implemented in FPGA (spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on CLA (28.49%), Vedic Multiplier based on RCA (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on HCA (20.10%) and Hybrid multiplier using CSELA (17.81%) and Hybrid Vedic Multiplier (7.15%).

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Design and Analysis of Area and Time Efficient Signed Square Architecture Using Nonconventional Method

Behera,

Pradhan,

Kumar Bhoi

2024

J CIRCUIT SYST COMP

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Computing the square of any large signed number using conventional methods is challenging. Therefore, parallel and partial product generation while squaring signed numbers is complex and time-consuming. This paper suggests a very large scale integration design for an efficient signed square architecture using a nonconventional method. The square of a large magnitude signed number is reduced to a lower magnitude signed multiplication and an addition operation by the Yavadunam algorithm. The suggested method finds the deficit of the signed number from the adjacent base to perform the signed square operation. The proposed design is coded using Verilog hardware description language. The synthesis and simulation of this architecture are performed using Xilinx integrated synthesis environment 14.7 software. Furthermore, this architecture is implemented on the Virtex-4, spartan-3 and spartan-6 field programmable gate array devices. The design is also coded in cadence virtuoso centos version 5. Then, it is synthesized using 180[Formula: see text]nm and 90[Formula: see text]nm technology. The validation of the proposed architecture is examined using the performance parameters, such as path delay and area. The synthesis results show improvements in delay-area complexity compared to state-of-the-art architectures. The superiority of the proposed architecture is claimed based on performance comparisons with the previous square, multipliers and signed multiplier architectures.

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FPGA implementation of proficient Vedic multiplier architecture using hybrid carry select adder

Cited by 3 publications

References 16 publications

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

Design of Efficient Binary Multiplier Architecture using Hybrid Compressor with FPGA implementation

Design and Analysis of Area and Time Efficient Signed Square Architecture Using Nonconventional Method

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