FPGA Implementation of RNS Adder Based MAC Unit in Ternary Value Logic Domain for Signal Processing Algorithm and its Performance Analysis

Ghosh, Aniruddha; Sinha, Amitabha

doi:10.1109/edkcon.2018.8770463

Cited by 5 publications

(3 citation statements)

References 27 publications

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“…The results given in [31] indicated the superiority of the ternary RNS compared to its weighted counterparts in the implementations of digital filters. Besides the abovementioned studies, some researches have been carried out for designing reverse converter for the moduli set…”

Section: Related Workmentioning

confidence: 92%

“…Based on the aforementioned redundant method, efficient modulo adders were also proposed in [29] and [30]. Furthermore, in [31], a novel architecture for multiply-accumulate (MAC) units for the moduli set {3 n − 2, 3 n − 1, 3 n } was proposed. This MAC unit was employed in the realization of DSP algorithms, such as FIR in the ternary domain.…”

Section: Related Workmentioning

confidence: 99%

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Fast and energy-efficient FPGA realization of RNS reverse converter for the ternary 3-moduli set {3n–2, 3n–1, 3n}

et al. 2020

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Ternary number representation has been known as one of the efficient methods for the implementation of digital systems. Employing residue number system (RNS) in ternary digital signal processing (DSP) applications could offer the advantages of ternary number representation along with further privileges such as improving parallelism and fault tolerance. Efficacious design of reverse converter as a crucial block of residue number system has always been of great interest to researchers. In this paper, an efficient reverse converter for ternary RNS with moduli set {3 n -2, 3 n -1, 3 n }, based on the mixed-radix conversion (MRC) algorithm is presented. The proposed algorithm reduces the number of adders with large bit-width and the dependencies between consecutively process blocks. The employed technique in the proposed algorithm and the reverse converter architecture improves the delay and area on the FPGA Virtex Ultrascale + family platform in 14 nm/16 nm FinFET technology as compared to the related works.

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Section: Related Workmentioning

confidence: 92%

Section: Related Workmentioning

confidence: 99%

Fast and energy-efficient FPGA realization of RNS reverse converter for the ternary 3-moduli set {3n–2, 3n–1, 3n}

et al. 2020

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“…The authors of [11] propose a method for constructing digital filters in RNS to automate the device design process and provide an effective ratio of speed and energy efficiency. In [12], a new architecture for multiply-accumulate (MAC) units are proposed, which are the basis of digital filters. The proposed architecture bases on ternary value logic and RNS, however using this approach leads to the high complexity of converting between ternary value logic and RNS.…”

Section: Introductionmentioning

confidence: 99%

Digital Filter Architecture With Calculations in the Residue Number System by Winograd Method F (2 × 2, 2 × 2)

et al. 2021

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Improving the technical characteristics of digital signal processing devices is an important problem in many practical tasks. The paper proposes the architecture of a device for two-dimensional filtering in a residue number system (RNS) with moduli of a special type according to the Winograd method. The work carried out the technical parameters theoretical analysis of the proposed filter architecture for different RNS moduli sets by the ''unit-gate''-model. In addition, the proposed architecture is compared with known digital filter implementations. The theoretical analysis results showed that the use of the proposed filter architecture makes it possible to increase the signal processing speed by 1.33 -6.90 times, in comparison with the known device implementations. Also, in the work, the hardware simulation of the proposed filter architecture was performed on FPGA, which showed that the performance of the proposed device is 1.31 -4.12 times higher than known digital filter architectures. The research results can be used in digital signal processing systems to increase their performance and reduce hardware costs. In addition, the developed architectures can be applied in the development of hardware accelerators for complex digital signals analysis systems.INDEX TERMS Digital filters, residue number system, Winograd method.

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Comparative Analysis for Conversion of Double Base Number System (DBNS) from Conventional Number System Using Binary Search Algorithm by Changing Base Patterns for ANN-Based Applications

Singha,

Ghosh

2024

Lecture Notes in Networks and Systems

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FPGA Implementation of RNS Adder Based MAC Unit in Ternary Value Logic Domain for Signal Processing Algorithm and its Performance Analysis

Cited by 5 publications

References 27 publications

Fast and energy-efficient FPGA realization of RNS reverse converter for the ternary 3-moduli set {3n–2, 3n–1, 3n}

Fast and energy-efficient FPGA realization of RNS reverse converter for the ternary 3-moduli set {3n–2, 3n–1, 3n}

Digital Filter Architecture With Calculations in the Residue Number System by Winograd Method F (2 × 2, 2 × 2)

Comparative Analysis for Conversion of Double Base Number System (DBNS) from Conventional Number System Using Binary Search Algorithm by Changing Base Patterns for ANN-Based Applications

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