FPGA Interconnect Topologies Exploration

Abstract

This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR-style Mesh.

Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA

“…The 3D Tree-based FPGA evaluation module includes a top-down recursive partitioning tool. The routing algorithm implemented is "Pathfinder" [12], which is an iterative, negotiation-based approach. The physical design experiments are performed based on the layout generated using ST Micro's 130nm technology node.…”

“…A new re-programmable Tree-based Multilevel FPGA architecture is proposed in [11]. The main motivation for the Tree-based FPGA architecture is to achieve the best performance by balancing interconnect and logic block utilization, where logic blocks and routing resources are sparsely partitioned into a multilevel clustered structure [12]. In a Tree-based FPGA architecture, the LBs (Logic Blocks) are grouped into clusters located at different levels of the Tree.…”

“…However this layout is not comparable to industrial Mesh layout in terms of speed and performance for larger circuits due to larger wire length at higher levels. Nevertheless this design can be used to build compact size and Mesh of Tree based FPGA [12].…”

“…The netlist is partitioned into tree based cluster nets attributing randomly to each cluster a position inside the owner. An iterative PathFinder which is, negotiation-based approach [12] is used to implement the placement and routing algorithm which is able to deal with any graph representing the interconnection routing resources. The 3D routing tool was adapted to handle the performance analysis of 2D and 3D layout with TSV interconnections, based on the 2 layer Tree-based FPGA.…”

Architecture level TSV count minimization methodology for 3D tree-based FPGA

“…Since FPGA is an interconnect dominated device, it is essential to minimize the TSV count because the TSVs consume more silicon area than horizontal interconnects. The TSV count optimization is performed using Rent's parameter [6] p defined for a Tree-based architecture shown in equation 1. The Tree level is represented as and k is the cluster arity, c is the number of in/out pins of an LB and IO is the number of in/out pins of a cluster located at level .…”