FPGAs for Improved Energy Efficiency in Processor Based Systems

Kwan, Pui-man.; Clarke, Christopher

doi:10.1007/11572961_35

Cited by 5 publications

(4 citation statements)

References 3 publications

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“…These devices were chosen as rapid prototyping platforms both because of their low cost compared to a custom ASIC and because at lower sampling rates an FPGA or CPLD can consume less power than an equivalent processor-based implementation [23]. Furthermore the relatively low sampling rates associated with ENG, typically less than 100 kS/s, may allow a reduction in core operating voltages and thus a saving in static power consumption in an FPGA [24].…”

Section: Power and Area Measurementsmentioning

confidence: 99%

A New Method for Neural Spike Alignment: The Centroid Filter

Metcalfe

Clarke

Donaldson

et al. 2017

IEEE Trans. Neural Syst. Rehabil. Eng.

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Highlights A key problem in neural spike sorting is highlighted.  A new method to measure the position of action potentials in real-time is described.  This method is validated using detailed simulations. Major improvements are demonstrated compared to standard methods. AbstractBackground: This paper describes a new method to calculate the positions of action potentials (APs) in extracellular neural recordings in real-time. Extracellular recordings made using various types of electrode structures are a key tool in experimental electrophysiology and involve the identification of signals from individual neurons, a process known by the generic name spike sorting. An essential feature of the process is the alignment of individual APs ('spikes') in time. Given the recordings are invariably made in noisy environments there is a tendency to timing jitter leading to alignment errors. This is especially true if single point methods of AP location are employed. New Method: The problems of single point AP location in the presence of noise are significantly reduced by the use of the centroid as a measure of position, which is based on a time average of all the points in the AP. The method is described and analysed in detail and it is shown that a very economical hardware realisation is possible. Results:The new methods are investigated by simulation using deterministic models of nerve signals (i.e. APs with added noise; both correlated and uncorrelated noise models are considered) as well as results measured from a hardware implementation. A power efficient realisation of the centroid filter is demonstrated using a complex programmable logic device (CPLD). Comparison with Existing Method:Detailed simulations demonstrate the superiority of the centroid method compared to several standard, single point metrics. Conclusions: A new method has been suggested that significantly improves one of the key issues in neural spike sorting. The technique has the potential to influence significantly the design of electrophysiological recording systems in the future.

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Section: Power and Area Measurementsmentioning

confidence: 99%

A New Method for Neural Spike Alignment: The Centroid Filter

Metcalfe

Clarke

Donaldson

et al. 2017

IEEE Trans. Neural Syst. Rehabil. Eng.

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“…Moreover, implementing algorithms as hardware circuitry instead of software code can be useful in devices where energy matters. Actually, a slow-clocked hardware implementation of an algorithm can offer the same performance as a higher speed software implementation, with less energy consumption [32]. Thus, reconfigurable hardware can improve energy efficiency of CPU-and GPU-based systems [30].…”

Section: Reconfigurable Hardwarementioning

confidence: 99%

Online codesign on reconfigurable platform for parallel computing

Foucher¹,

Muller²,

Giulieri³

2013

Microprocessors and Microsystems

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International audienceReconfigurable hardware offers new ways of accelerating computing by implementing hardware accelerators at run time. In this article, we present an approach allowing a hardware/software codesign of applications in which implementation can be chosen at run time depending on available resources. We propose a platform supporting this flow and describe its different implementations used to prove the feasibility of our approach. This platform allows the underlying hardware to be virtualized in order to have a generic architecture that can be used to run applications. Partial dynamic reconfiguration is used over Xilinx Virtex 5 boards to enhance reconfiguration capabilities

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“…Contemporary literature estimates that commercially-available FPGAs are 8-88X worse in area, 2-14X in delay, and 12-500X in power relative to even a standard-cell ASIC design [18]. Often worse are fetchexecute processors, which can be orders of magnitude less efficient in energy and delay than FPGA implementations [19,24].…”

Section: Introductionmentioning

confidence: 99%

On the asymptotic costs of multiplexer-based reconfigurability

York

Chiou

2012

Proceedings of the 49th Annual Design Automation Conference

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Existing literature documents a number of techniques for combining a set of independent datapath designs into a single datapath that is run-time configurable to the functionality of any datapath in the set. This paper explores how delay, energy and area overhead attributable to reconfigurability scales with the number of configurable functionalities, independent of the design of specific datapaths. Distinct design space regions are identified based upon common scaling properties, with implications on the design and feasible efficiency bounds of reconfigurable devices.

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FPGAs for Improved Energy Efficiency in Processor Based Systems

Cited by 5 publications

References 3 publications

A New Method for Neural Spike Alignment: The Centroid Filter

A New Method for Neural Spike Alignment: The Centroid Filter

Online codesign on reconfigurable platform for parallel computing

On the asymptotic costs of multiplexer-based reconfigurability

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