Fuzzy inference and fuzzy inference processor

Nakamura, Kazuo; Sakashita, N.; Nitta, Yoshikazu; Shimomura, K.; Tokuda, T.

doi:10.1109/40.238000

Cited by 55 publications

(12 citation statements)

References 6 publications

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“…xcellent 的次数,并且有: 假设 P 表值.构件执行结束后,属性 P 的 compliance 值 C p 如下计算: 在推理过程 max 模糊推理方法 [10] ,规则的输出使用 fuzzy union 方法进行聚合,得到最终的服务能力模糊集表示.…”

Section: 定义 2(构件服务质量分级评估模型unclassified

A Dynamic QoS Assessment Approach for Internetware with Uncertainty Reasoning

Wu¹

2008

Journal of Software

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This paper proposes a dynamic QoS assessment approach for Internetware with uncertainty reasoning.The salient feature of this approach is that it's based on Bayesian network, and can correctly predict the component's service capability in various combinations of users' QoS requirements, especially to the entities with different service levels. Through online learning, it supports to update the Bayesian network dynamically and improves the accuracy of prediction result. The proposed QoS assessment model has been implemented in the developed Service Coordination Bus (Once-ESB). The experimental results show that it is effective.

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Section: 定义 2(构件服务质量分级评估模型unclassified

A Dynamic QoS Assessment Approach for Internetware with Uncertainty Reasoning

Wu¹

2008

Journal of Software

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“…Recently, there has been a spread of solutions on VLSI chips which allow fuzzy inferences to be hardware-computed [10,11]. There are also several architectural proposals which allow the hardware resources to be implemented on chips to be chosen in such a way as to obtain a certain cost/performance ratio [12±14].…”

Section: Design Of a Vlsi Architecture For The Fuzzy Priority Controlmentioning

confidence: 99%

An efficient fuzzy system for traffic management in high-speed packet-switched networks

2001

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In this paper we present a novel buffer management scheme based on fuzzy logic. We deal with the problem of managing traf®c¯ows with different priorities within the same buffer. The aim is to guarantee the QoS of high-priority traf®c, and at the same time exploit unused buffer resources to accommodate best-effort traf®c in order to maximize the total throughput. The scheme we propose can be applied both to ATM and IP networks. The performance evaluation of the fuzzy priority control scheme shows that it outperforms any static threshold mechanism and, as far as the total throughput is concerned, it is very close to that of the push out mechanism considered in literature as an ideal mechanism. Finally, we address some implementation issues of the control system and propose the design of a new cost-effective VLSI fuzzy processor.

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“…This error can be attenuated by proper setting of the bias voltage of the cascode transistor For optimum attenuation, this voltage should be different for different input values. However, system-level considerations [27] show that it suffices to obtain the largest possible error attenuation at the 6 They will be modeled through an equivalent Early voltage V A which is a quasi-linear function of the channel length [26]. crossover points.…”

Section: ) Membership Function Circuitmentioning

confidence: 99%

“…The normalization circuit does not contribute either because appears at the numerator and the denominator in (23) and (24). The membership function circuit is the only whose transfer function [given by (6)] depends on temperature. However, the electrical values of the logical zero and one are not affected, provided the current reference is temperature-independent, because these values are associated to logical states of the transistors in the differential pairs.…”

Section: A Dependence On Temperaturementioning

confidence: 99%

A modular programmable CMOS analog fuzzy controller chip

Rodríguez-Vázquez

Navas

Delgado‐Restituto

et al. 1999

IEEE Trans. Circuits Syst. II

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Abstract-We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital programmability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely label blocks and rule blocks. The architecture realizes a lattice partition of the universe of discourse, which at the hardware level means that the fuzzy labels associated to every input (realized by the label blocks) are shared among the rule blocks. This reduces the area and power consumption and is the key point for chip modularity. The proposed architecture is demonstrated through a 16-rule twoinput CMOS 1-m prototype which features an operation speed of 2.5 Mflips (2.5 2 2 2 10 6 fuzzy inferences per second) with 8.6 mW power consumption. Core area occupation of this prototype is of only 1.6 mm 2 including the digital control and memory circuitry used for programmability. Because of the architecture modularity the number of inputs and rules can be increased with any hardly design effort.

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Fuzzy inference and fuzzy inference processor

Cited by 55 publications

References 6 publications

A Dynamic QoS Assessment Approach for Internetware with Uncertainty Reasoning

A Dynamic QoS Assessment Approach for Internetware with Uncertainty Reasoning

An efficient fuzzy system for traffic management in high-speed packet-switched networks

A modular programmable CMOS analog fuzzy controller chip

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