Gate-Drain Charge Analysis for Switching in Power Trench MOSFETs

Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor

“…Investigation of Laterally Single-diffused Metal Oxide Semiconductor (LSMOS) Field Effect Transistor 7 LDMOS to have a better gate control and that of C GD should be less as it acts as a miller capacitance [32][33][34]. The calculated value of C GS and C GD for the LSMOS are 12.7 nF/mm 2 and 2206.1 nF/mm 2 and for the LDMOS are 12.9 nF/mm 2 and 1260.4 nF/mm 2 , respectively.…”

Modeling the Impact of the Trench Depth on the Gate–Drain Capacitance in Power MOSFETs

“…1 shows the cross-sectional image of a trench MOSFET and a schematic illustrating the terminal capacitances inherent in the design. Since increasing the trench depth increases the gate-drain overlap, it is expected to cause higher C GD and has been demonstrated to do so by previous studies [2]. To mitigate this, concepts like the thick bottom oxide (TBO), the W-gated trench [3] and the split gate have been developed to reduce C GD without compromising on the conduction loss benefit of the trench structure.…”

A Trench Gate Power MOSFET with Reduced Gate Charge - A Review

“…Various disadvantages of a Trench MOSFET include switching delays mainly due to the gate charge [5]. Hence, if the gate charge is reduced without changing onresistance much, the switching speed can be increased [3]. This is done in the proposed MOSFET by introducing an n + -p junction in the gate of the MOSFET.…”