Gate isolation technology for compact poly-CMP embedded flash memories

Slotboom, M.; Goarin, P.; Akil, N.; Duuren, M. van; Demand, M.; Wouters, Jan; Beckx, S.; Leray, Philippe; Baertsb, C.; Baerts, C.; Heylen, N.; Pollentier, Ivan

doi:10.1109/essderc.2003.1256835

Cited by 6 publications

(2 citation statements)

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“…19) These process issues cause the leakage between the FG and the AG in the split-gate flash memory, and studies of gap oxide technologies have been performed to prevent them. [19][20][21] In the proposed S4-NOR, it is possible to reduce L gap without suffering from the above-mentioned process issues in conventional split-gate structures, because both the AG and the FG are patterned simultaneously. The key process steps for gap oxide formation in S4-NOR are shown in Fig.…”

Section: Cell Structure and Process Technologymentioning

confidence: 99%

Source-side injection single-polysilicon split-gate flash memory

Yamauchi

Kamakura

Matsuoka

et al. 2014

Jpn. J. Appl. Phys.

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The source-side injection single-polysilicon split-gate NOR (S4-NOR) flash memory is proposed for embedded applications. For the S4-NOR cell, the access and floating gates are patterned on the channel between the source and drain junctions with a gap length of 55 nm using conventional photolithography technology, and the floating gate is capacitively coupled to an n-well memory gate. This technology can improve the compatibility with a single-polysilicon CMOS logic process. The memory cell is programmed within 5 µs with a low drain current of 10 µA, and its program efficiency is insensitive to process parameters except gap length, which are suitable for embedded memories from the process control viewpoint in addition to low power consumption. Good reliability is also realized without the effect of gap oxide leakage. Furthermore, the performance and reliability of the S4-NOR cell can be improved by scaling the logic process without using any special process.

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Section: Cell Structure and Process Technologymentioning

confidence: 99%

Source-side injection single-polysilicon split-gate flash memory

Yamauchi

Kamakura

Matsuoka

et al. 2014

Jpn. J. Appl. Phys.

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“…While some technologies of producing flash memory are not mature enough to enable an efficient and high performance manufacturing. In manufacturing flash memories, one of the most important processes is forming floating gate or control gate, whose final performance is greatly influenced by Gate-poly CMP performance [2]. As shown in Figure 1, to prepare a floating gate or control gate, the removal of an overburdened poly film layer deposited on HDP oxide film is needed, leaving no poly residue on the top of HDP surface and a certain thickness of Active Area (AA) poly whose top surface is ideally planar with HDP top surface.…”

Section: Introductionmentioning

confidence: 99%

Poly-CMP Slurry for Flash Memories

Jing

Chiu²,

Huang³

et al. 2009

ECS Trans.

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IC market demand for flash memories showed a significant growth trend in recent years. In manufacturing of flash memories, one of the most important processes is forming floating gate or control gate, which is greatly influenced by gate-poly CMP performance. To prepare a floating gate or control gate, a poly-silicon (poly) layer will be deposited on the active area (AA) , which is between the STI trench structures, typically HDP oxide. Then through CMP technique, the overburdened poly will be removed, with no poly residue on the top of HDP surface and leaving a certain thickness of AA poly whose top surface is planar with HDP top surface. However, in the case that a poly layer and a silicon dioxide layer are being polished, the removal rate of poly-silicon will tend to be much higher than that of silicon dioxide, resulting in recess between the STI trench structures and a non-planarized surface. To overcome this issue, we report here a novel poly CMP slurry that has the self-stopping capability and good planarization efficiency, with which the excellent surface planarity, poly dishing and poly residue clearance were obtained on 300 mm patterned wafers.

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