Gate usage strategies applied to BiCMOS sea-of-gates arrays

Abstract

Strategies for CMOS and BiCMOS gate usage are examined. Taking into account the copacirive load and fm-in dktributionr, the infruence on the gate de@ and m a b cxmnined, and o p W ratios are derived. Those results are applied to the design of a BiCUOS sea-ofigates array.