General Reuse-Centric CNN Accelerator

Cicek, Nihat Mert; Lin, Ning; Öztürk, Özcan; Shen, Xipeng

doi:10.1109/tc.2021.3064608

Cited by 8 publications

(1 citation statement)

References 46 publications

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“…However, the lightweight CNN model contains a variety of kernel sizes, which challenges the design of FPGA-based CNN accelerators. Most existing designs [12][13][14][15][16][17][18][19][20][21] can effectively handle the convolution with some specified kernel sizes. However, when the kernel size changes, the utilization of PE units in the computation array is significantly reduced.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of an efficient CNN accelerator for low-cost FPGAs

Wang

et al. 2022

IEICE Electron. Express

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This paper proposes a computation-array-centered dataflow, which adjusts the convolution with different kernel sizes to a unified computing manner and reduces the dimension of computation array from 2D to 1D, so as to maximize the utilization of the computation elements offered by the accelerator. Furthermore, a single unit multiple data (SUMD) strategy is proposed to effectively alleviate the mismatch between the quantized data and the hardware resources with fixed bit width on FPGA. As a case study, an 8-bit MobileNetV2 model has been implemented on the low-cost ZYNQ XC7Z020 FPGA, whose FPS/DSP and GOPS/DSP achieve upto 0.55 and 0.35 respectively.

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