Generalized diamond‐type single DC‐source switched‐capacitor based multilevel inverter with step‐up and natural voltage balancing capabilities

Abstract

This paper proposes a diamond‐shaped high step‐up switched‐capacitor based basic multilevel inverter topology. The basic switched‐capacitor (SC) stage consists of 2 active switches, 2 diodes, and 2 capacitors. Using a single DC source with the unfolding circuit (10 switches, 5 capacitors, and 5 diodes) results in the production of 17 voltage‐steps at the output with the gain of up to 8 times of the input voltage. By extending the diamond‐shaped switched‐capacitor stages, higher voltage levels and voltage gains can be possible. The suggested topology employs two half‐bridges (instead of a full‐bridge) to produce positive, zero, and negative steps, which reduces the Voltage Stress (VS) on two output switches and consequently reduces Total Voltage Stress (TVS). In addition, the natural voltage balancing of capacitors eliminates the need to an additional control circuitry and consequently reduces the total converter size, complexity, and cost. In addition, modularity, scalability, low voltage ripple on capacitors, low total voltage stress, high power quality, and capability of supplying low/medium power factor (R‐L) loads are some of the merits of the proposed topology. The low Cost Function (CF) obtained in the comparison section as well as experimental results verifies the advantages of the proposed topology.

Hybrid 17‐level inverters based on T‐type flying‐capacitor and switched‐capacitor

“…In this section, the proposed hybrid MLIs with the two SCVLs of Figure 1 are referred as PHIa and PHIb, and they are compared with other 17‐level MLIs with similar structure in terms of the numbers of output levels N L , dc source N s , transistors N t , diodes N d , capacitors N c and gate drivers N dr , the TSV of switches, the total capacitor voltage (TCV), the cost function (CF), and the boost factor (BF). The CF introduced in previous works 20,22,23 is used in this work to estimate the total cost of each structure. Note that, the CF is defined by where α 1 and α 2 are the weight coefficients for TSC and TCV, and both of them are set to 1 for convenience.…”

“…The comparison results are illustrated in Table 3. The 17‐level inverters presented in previous studies 5,6,8,22,23 have the advantages of high voltage gain and low cost for unity gain. However, they use more switching devices and capacitors to generate 17 levels of the output voltage.…”

“…Especially, four high‐voltage transistors are required in Hinago and Koizumi 5 and Ye et al 6 for the inverting H‐bridge. Although it is reduced by half in Saeedian et al 8 and Deliri et al, 23 multiple high‐voltage capacitors are used and the problem of capacitor voltage ripple accumulation is very serious in these MLIs. All components used in Taghvaie et al 22 withstand the same voltage stress of E , but too many transistors are employed.…”

A new high‐level boost inverter topology with reduced device count

“…In Sharifzadeh and Al‐Haddad, [ 13 ] a packed E cell topology has been proposed having the basic idea from PUC which lacked the boosting feature. In the topology of Deliri et al, [ 14 ] a hybrid topology with a diamond shape structure has been proposed which can generate 17 levels of the voltage with a single source configuration. It uses five capacitors with five diodes and 10 switches for 17 levels with a voltage gain of 8.…”

A Dual Source Switched-Capacitor Multilevel Inverter with Reduced Device Count

“…A topology using two asymmetrical dc sources, four capacitors and ten switches is presented in [16] with a specific method for capacitor charge balancing. More examples of multiple dc source topologies with reduced device count and self-balancing capabilities can be observed as in [25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41].…”